LC4064ZE-7MN64I Lattice, LC4064ZE-7MN64I Datasheet - Page 27

• Manufacturer Part Number: LC4064ZE-7MN64I
• Description: CPLD - Complex Programmable Logic Devices 64MC 48 I/O Low Pwr 1.8V 7.5ns
• Manufacturer: Lattice
• Series: ispMACH®r

Specifications of LC4064ZE-7MN64I

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Maximum Operating Frequency: 178.57 MHz
• Delay Time: 7.5 ns
• Number Of Programmable I/os: 48
• Operating Supply Voltage: 1.8 V
• Supply Current: 0.08 mA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Package / Case: CSBGA
• Mounting Style: SMD/SMT
• Supply Voltage (max): 1.9 V
• Supply Voltage (min): 1.7 V
• Programmable Type: CPLD
• Voltage - Input: 1.7 V ~ 1.9 V
• Speed: 7.5ns
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispMACH 4000ZE Internal Timing Parameters (Cont.)
Lattice Semiconductor
In/Out Delays
t
t
t
t
t
t
t
t
t
t
Routing Delays
t
t
t
t
t
t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
GCLK_IN
GOE
BUF
EN
DIS
PGSU
PGH
PGPW
PGRT
ROUTE
PDi
MCELL
INREG
FBK
ORP
S
S_PT
H
ST
ST_PT
HT
SIR
SIR_PT
HIR
HIR_PT
COi
CES
CEH
SL
SL_PT
HL
GOi
PDLi
SRi
Parameter
Input Buffer Delay
Global Clock Input Buffer Delay
Global OE Pin Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
Input Power Guard Setup Time
Input Power Guard Hold Time
Input Power Guard BIE Minimum Pulse Width
Input Power Guard Recovery Time Following BIE Dis-
sertation
Delay through GRP
Macrocell Propagation Delay
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
Output Routing Pool Delay
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
D-Register Hold Time
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
T-Resister Hold Time
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
Propagation Delay through Transparent Latch to Output/
Feedback MUX
Asynchronous Reset or Set to Output/Feedback MUX
Delay
Over Recommended Operating Conditions
Description
27
ispMACH 4000ZE Family Data Sheet
Min.
0.90
2.00
2.00
1.10
2.20
2.00
1.20
1.45
1.40
1.10
2.00
0.00
0.90
2.00
2.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
1.05
1.95
3.00
1.10
2.50
2.50
4.30
0.00
6.00
5.00
2.25
0.45
0.65
1.00
0.75
0.30
0.45
0.35
0.25
0.95
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All Devices
Min.
1.25
2.35
3.25
1.45
2.65
3.25
0.65
1.45
2.05
1.20
2.00
0.00
1.55
2.05
1.17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
Max.
1.90
2.15
4.30
1.30
2.70
2.70
5.60
0.00
8.00
7.00
2.50
0.50
1.00
1.00
0.30
0.30
0.75
0.33
0.25
0.28
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns