A3P600L-FGG484 Actel, A3P600L-FGG484 Datasheet - Page 53
A3P600L-FGG484
Manufacturer Part Number
A3P600L-FGG484
Description
FPGA - Field Programmable Gate Array 6K SYSTEM GATES
Manufacturer
Actel
Datasheet
1.A3P250L-VQG100.pdf
(224 pages)
Specifications of A3P600L-FGG484
Processor Series
A3P600
Core
IP Core
Maximum Operating Frequency
781.25 MHz
Number Of Programmable I/os
235
Data Ram Size
110592
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P600L-FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P600L-FGG484
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A3P600L-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-45 • Minimum and Maximum DC Input and Output Levels
Table 2-46 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
3.3 V LVTTL /
3.3 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low voltage transistor–transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all
LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8a
specification.
Applicable to Pro I/O Banks
Applicable to Advanced I/O Banks
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Min.
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
VIL
VIL
Max.
0.8
0.8
0.8
0.8
0.8
0.8
V
Max.
0.8
0.8
0.8
0.8
0.8
0.8
0.8
V
Min.
V
2
2
2
2
2
2
Min.
V
2
2
2
2
2
2
2
VIH
VIH
Max.
3.6
3.6
3.6
3.6
3.6
3.6
V
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
Max.
VOL
0.4
0.4
0.4
0.4
0.4
0.4
V
R e v i s i o n 9
Max.
VOL
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V
VOH
Min.
2.4
2.4
2.4
2.4
2.4
2.4
V
VOH
Min.
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V
mA mA
I
24 24
OL
12 12
16 16
24 24
4
8
mA mA
I
I
24
OH
OL
12
16
2
6
4
8
4
8
I
24
OH
12
16
2
6
4
8
ProASIC3L Low Power Flash FPGAs
Max.
mA
I
103
132
268
OSL
25
51
27
Max.
1
mA
I
103
132
268
OSL
25
25
51
51
1
Max.
I
mA
109
127
181
OSH
Max.
mA
I
27
54
25
109
127
181
OSH
27
27
54
54
1
1
µA
µA
I
10
10
10
10
10
10
10
10
I
10
10
10
10
10
IL
IL
2
2
µA
µA
I
2- 39
I
10
10
10
10
10
10
10
10
10
10
10
10
10
IH
IH
2
2
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