A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 37

• Manufacturer Part Number: A54SX08A-TQG100
• Description: FPGA - Field Programmable Gate Array 12K System Gates
• Manufacturer: Actel

Specifications of A54SX08A-TQG100

• Processor Series: A54SX08
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 130
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 8000
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Characteristics
Timing characteristics for SX-A devices fall into three
categories: family-dependent, device-dependent, and
design-dependent.
characteristics are common to all SX-A family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. The timing characteristics listed in this
datasheet represent sample timing numbers of the SX-A
devices. Design-specific delay values may be determined
by using Timer or performing simulation after successful
place-and-route with the Designer software.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most
timing-critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are
typical.
Temperature and Voltage Derating Factors
Table 2-13 • Temperature and Voltage Derating Factors
V
2.250 V
2.500 V
2.750 V
CCA
(Normalized to Worst-Case Commercial, T
–55°C
0.79
0.74
0.68
The
input
–40°C
0.80
0.75
0.69
and
output
0.87
0.82
0.75
0°C
buffer
J
Junction Temperature (T
= 70°C, V
v5.3
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules.
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6 percent of
nets in a fully utilized device require long tracks. Long
tracks contribute approximately 4 ns to 8.4 ns delay. This
additional delay is represented statistically in higher
fanout routing delays.
Timing Derating
SX-A devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum
processing.
minimum
temperature, and worst-case processing.
CCA
25°C
0.89
0.83
0.77
= 2.25 V)
operating
operating
Maximum
J
70°C
)
1.00
0.94
0.87
Long tracks employ three to five
voltage,
temperature,
timing
85°C
1.04
0.97
0.90
maximum
parameters
SX-A Family FPGAs
and
125°C
operating
1.14
1.07
0.99
best-case
reflect
2-17