A54SX08A-TQG100 Actel, A54SX08A-TQG100 Datasheet - Page 9

• Manufacturer Part Number: A54SX08A-TQG100
• Description: FPGA - Field Programmable Gate Array 12K System Gates
• Manufacturer: Actel

Specifications of A54SX08A-TQG100

• Processor Series: A54SX08
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 130
• Delay Time: 4 ns to 8.4 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 8000
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Resources
Actel’s high-drive routing structure provides three clock
networks
hardwired from the HCLK buffer to the clock select
multiplexor (MUX) in each R-cell. HCLK cannot be
connected to combinatorial logic. This provides a fast
propagation path for the clock signal. If not used, this
pin must be set as Low or High on the board. It must not
be left floating.
used for the constant load HCLK and the macros
supported.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Design
software and the pin must be tied to GND on the board.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the SX-A device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB pins are not used or sourced from signals,
these pins must be set as Low or High on the board. They
must not be left floating.
Table 1-1 • SX-A Clock Resources
Figure 1-7 • SX-A HCLK Clock Buffer
Figure 1-8 • SX-A Routed Clock Buffer
Routed Clocks (CLKA, CLKB)
Hardwired Clocks (HCLK)
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)
(Table
1-1). The first clock, called HCLK, is
Figure 1-7
Figure 1-8
describes the clock circuit
describes the CLKA
HCLKBUF
A54SX08A
CLKBUF
CLKBUFI
CLKINT
CLKINTI
2
1
0
v5.3
and CLKB circuit used and the macros supported in SX-A
devices with the exception of A54SX72A.
In addition, the A54SX72A device provides four
quadrant clocks (QCLKA, QCLKB, QCLKC, and QCLKD—
corresponding to bottom-left, bottom-right, top-left,
and top-right locations on the die, respectively), which
can be sourced from external pins or from internal logic
signals within the device. Each of these clocks can
individually drive up to an entire quadrant of the chip,
or they can be grouped together to drive multiple
quadrants
function as user I/O pins. If not used, the QCLK pins
must be tied Low or High on the board and must not be
left floating.
For more information on how to use quadrant clocks in
the A54SX72A device, refer to the
in Actel’s Antifuse Devices
RT54SX72S Quadrant Clocks
The CLKA, CLKB, and QCLK circuits for A54SX72A as well
as the macros supported are shown in
page
available in A54SX72A. For more information, refer to
the
Constant Load
Clock Network
"Pin Description" section on page
1-6. Note that bidirectional clock buffers are only
A54SX16A
From Internal Logic
(Figure 1-9 on page
Clock Network
2
1
0
A54SX32A
application notes.
and
2
1
0
Global Clock Networks
Using A54SX72A and
1-6). QCLK pins can
SX-A Family FPGAs
1-15.
Figure 1-10 on
A54SX72A
2
1
4
1-5