AGL400V5-FGG256 Actel, AGL400V5-FGG256 Datasheet - Page 103
![FPGA - Field Programmable Gate Array 400K System Gates](/photos/16/15/161508/fgba-256_sml.jpg)
AGL400V5-FGG256
Manufacturer Part Number
AGL400V5-FGG256
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL400V5-FGG256
Processor Series
AGL400
Core
IP Core
Number Of Logic Blocks
12
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
178
Data Ram Size
54 Kbit
Supply Voltage (max)
1.5 V
Supply Current
27 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGL400V5-FGG256
Manufacturer:
Actel
Quantity:
135
Part Number:
AGL400V5-FGG256
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
AGL400V5-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL400V5-FGG256I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
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Figure 2-18 • Input Register Timing Diagram
Table 2-156 • Input Data Register Propagation Delays
Enable
Data
Clear
CLK
Preset
Out_1
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
Input Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
50%
1.5 V DC Core Voltage
50%
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
ICLKQ
t
IHD
50%
50%
50%
J
t
IWPRE
= 70°C, Worst-Case VCC = 1.425 V
t
IPRE2Q
Description
50%
50%
R ev i si o n 1 8
t
IRECPRE
50%
t
ICLR2Q
50%
t
IWCLR
50%
50%
50%
t
Table 2-6 on page 2-7
IRECCLR
50%
IGLOO Low Power Flash FPGAs
t
ICKMPWH
t
IREMPRE
50%
for derating values.
50%
t
ICKMPWL
0.42
0.47
0.00
0.67
0.00
0.79
0.79
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
50%
t
50%
IREMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 89
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