AGL400V5-FGG256 Actel, AGL400V5-FGG256 Datasheet - Page 119
![FPGA - Field Programmable Gate Array 400K System Gates](/photos/16/15/161508/fgba-256_sml.jpg)
AGL400V5-FGG256
Manufacturer Part Number
AGL400V5-FGG256
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.AGL030V2-CSG81.pdf
(236 pages)
Specifications of AGL400V5-FGG256
Processor Series
AGL400
Core
IP Core
Number Of Logic Blocks
12
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
178
Data Ram Size
54 Kbit
Supply Voltage (max)
1.5 V
Supply Current
27 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AGL400V5-FGG256
Manufacturer:
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Quantity:
135
Part Number:
AGL400V5-FGG256
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
AGL400V5-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
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Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
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Table 2-171 • Register Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
For specific junction temperature and voltage supply levels, refer to
1.2 V DC Core Voltage
Commercial-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i si o n 1 8
Table 2-7 on page 2-7
IGLOO Low Power Flash FPGAs
for derating values.
1.61
1.17
0.00
1.29
0.00
0.87
0.89
0.00
0.24
0.00
0.24
0.46
0.46
0.95
0.95
Std.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 105
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