AGLN010V5-UCG36 Actel, AGLN010V5-UCG36 Datasheet - Page 56
![FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano](/photos/16/15/161509/uc-36_sml.jpg)
AGLN010V5-UCG36
Manufacturer Part Number
AGLN010V5-UCG36
Description
FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN010V5-UCG36
Processor Series
AGLN010
Core
IP Core
Number Of Macrocells
86
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
23
Supply Voltage (max)
1.5 V
Supply Current
3 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
10 K
Package / Case
uCSP-36
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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IGLOO nano DC and Switching Characteristics
Table 2-70 • Parameter Definition and Measuring Nodes
2- 42
Parameter Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
OCLKQ
OSUD
OHD
OPRE2Q
OREMPRE
ORECPRE
OECLKQ
OESUD
OEHD
OEPRE2Q
OEREMPRE
OERECPRE
ICLKQ
ISUD
IHD
IPRE2Q
IREMPRE
IRECPRE
See
Figure 2-12 on page 2-41
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
for more information.
Parameter Definition
R ev i sio n 1 1
Measuring Nodes
(from, to)*
H, DOUT
H, EOUT
L, DOUT
I, EOUT
C, A
C, A
D, E
D, A
F, H
L, H
L, H
J, H
A, E
D, A
F, H
J, H
I, H
I, H
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