AGLN010V5-UCG36 Actel, AGLN010V5-UCG36 Datasheet - Page 77
![FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano](/photos/16/15/161509/uc-36_sml.jpg)
AGLN010V5-UCG36
Manufacturer Part Number
AGLN010V5-UCG36
Description
FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN010V5-UCG36
Processor Series
AGLN010
Core
IP Core
Number Of Macrocells
86
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
23
Supply Voltage (max)
1.5 V
Supply Current
3 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
10 K
Package / Case
uCSP-36
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Global Resource Characteristics
Figure 2-25 • Example of Global Tree Use in an AGLN125 Device for Clock Routing
CCC
AGLN125 Clock Tree Topology
Clock delays are device-specific.
global tree presented in
It is used to drive all D-flip-flops in the device.
Figure 2-25
Figure 2-25
is driven by a CCC located on the west side of the AGLN125 device.
R ev i si o n 1 1
is an example of a global tree used for clock routing. The
IGLOO nano Low Power Flash FPGAs
Central
Global Rib
VersaTile
Rows
Global Spine
2- 63
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