A3P250-FGG256 Actel, A3P250-FGG256 Datasheet - Page 115
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A3P250-FGG256
Manufacturer Part Number
A3P250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P250-FGG256
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250-FGG256
Manufacturer:
ACT
Quantity:
89
Company:
Part Number:
A3P250-FGG256
Manufacturer:
ACTEL
Quantity:
1 400
Company:
Part Number:
A3P250-FGG256I
Manufacturer:
ACTEL
Quantity:
7 204
Company:
Part Number:
A3P250-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P250-FGG256T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-117 • RAM512X18
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
DS
DH
CKQ1
CKQ2
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same
address—Applicable to Opening Edge
Address collision clk-to-clk delay for reliable write access after read on same
address— Applicable to Opening Edge
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
Description
J
= 70°C, Worst-Case VCC = 1.425 V
R e v i s i o n 9
Table 2-6 on page 2-6
ProASIC3 Flash Family FPGAs
0.25 0.28 0.33
0.00 0.00 0.00
0.13 0.15 0.17
0.10 0.11 0.13
0.18 0.21 0.25
0.00 0.00 0.00
2.16 2.46 2.89
0.90 1.02 1.20
0.50 0.43 0.38
0.59 0.50 0.44
0.92 1.05 1.23
0.92 1.05 1.23
0.29 0.33 0.38
1.50 1.71 2.01
0.21 0.24 0.29
3.23 3.68 4.32
310
–2
for derating values.
272
–1
Std. Units
231
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 101