A3P250-FGG256 Actel, A3P250-FGG256 Datasheet - Page 75
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A3P250-FGG256
Manufacturer Part Number
A3P250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P250-FGG256
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250-FGG256
Manufacturer:
ACT
Quantity:
89
Company:
Part Number:
A3P250-FGG256
Manufacturer:
ACTEL
Quantity:
1 400
Company:
Part Number:
A3P250-FGG256I
Manufacturer:
ACTEL
Quantity:
7 204
Company:
Part Number:
A3P250-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A3P250-FGG256T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-78 • Minimum and Maximum DC Input and Output Levels
Figure 2-9 • AC Loading
Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads
1.5 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = V
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Applicable to Standard I/O Banks
Min.
–0.3
V
Test Point
Datapath
0.35 * VCCI 0.65 * VCCI
VIL
trip.
Max.
V
See
Table 2-22 on page 2-22
35 pF
Input High (V)
Min.
V
VIH
1.5
Enable Path
Max.
Test Point
3.6
V
R = 1 k
0.25 * VCCI 0.75 * VCCI
for a complete table of trip points.
R e v i s i o n 9
Max.
VOL
V
Measuring Point* (V)
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
0.75
VOH
Min.
V
HZ
ZH
/ t
/ t
LZ
HZ
mA mA
LZ
I
ZHS
OL
2
/ t
/ t
ZL
ZH
I
/ t
OH
2
ZL
ProASIC3 Flash Family FPGAs
/ t
/ t
ZLS
ZHS
/ t
Max.
mA
I
OSL
13
ZLS
C
3
LOAD
Max.
I
mA
OSH
35
16
(pF)
3
µA
I
IL
10
1
4
µA
I
2- 61
IH
10
2
4