AGLN010V2-UCG36 Actel, AGLN010V2-UCG36 Datasheet - Page 61

• Manufacturer Part Number: AGLN010V2-UCG36
• Description: FPGA - Field Programmable Gate Array 10K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN010V2-UCG36

• Processor Series: AGLN010
• Core: IP Core
• Number Of Macrocells: 86
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 23
• Supply Voltage (max): 1.5 V
• Supply Current: 3 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 10 K
• Package / Case: uCSP-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-15 • Output Register Timing Diagram
Table 2-74 • Output Data Register Propagation Delays
Data_out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
Preset
DOUT
Clear
CLK
For specific junction temperature and voltage supply levels, refer to
Output Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
1.5 V DC Core Voltage
50%
1
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
J
50%
= 70°C, Worst-Case VCC = 1.425 V
50%
Description
t
OWPRE
t
OPRE2Q
50%
50%
R ev i si o n 1 1
t
ORECPRE
t
50%
OCLR2Q
50%
t
OWCLR
50%
50%
50%
Table 2-6 on page 2-6
t
ORECCLR
IGLOO nano Low Power Flash FPGAs
50%
t
OCKMPWH
t
50%
OREMPRE
for derating values.
t
50%
OCKMPWL
1.00
0.51
1.34
1.34
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
0.00
t
OREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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