LFE3-150EA-7FN672CTW Lattice, LFE3-150EA-7FN672CTW Datasheet - Page 34

• Manufacturer Part Number: LFE3-150EA-7FN672CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN672CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-672
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O buffers as shown in Figure 2-32. The PIO Block
supplies the output data (DO) and the tri-state control signal (TO) to the sysI/O buffer and receives input from the
buffer. Table 2-11 provides the PIO signal list.
Figure 2-32. PIC Diagram
ECLK1, ECLK2
* Signals are available on left/right/top edges only.
** Signals are available on the left and right sides only
*** Selected PIO.
DYNDEL[7:0]
DCNTL[5:0]
ONEGA**
ONEGB**
PRMDET
DEL[3:0]
ONEGB
OPOSA
OPOSB
ECLK1
ECLK2
GSRN
READ
SCLK
SCLK
INDD
INCK
DQSI
LSR
INB
IPB
INA
IPA
CE
TS
Control
Muxes
CEOT
GSR
CLK
LSR
CEI
I/Os in a DQS-12 Group, Except DQSN (Complement of DQS) I/Os
(One per DQS Group of 12 I/Os)***
DQS Control Block
Read Control
Write Control
2-31
DDRCLKPOL*
PIOA
ECLKDQSR*
Register
Register
Tristate
Register
Output
Block
Block
Block
PIOB
DDRLAT*
DQCLK0*
DQCLK1*
(ISI)
Input
DQSW*
IOLD0
IOLT0
DI
LatticeECP3 Family Data Sheet
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture