LFE3-150EA-7FN672CTW Lattice, LFE3-150EA-7FN672CTW Datasheet - Page 46

• Manufacturer Part Number: LFE3-150EA-7FN672CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN672CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-672
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
On-Chip Programmable Termination
The LatticeECP3 supports a variety of programmable on-chip terminations options, including:
Figure 2-39. On-Chip Termination
See Table 2-12 for termination options for input modes.
Table 2-12. On-Chip Termination Options for Input Modes
• Dynamically switchable Single Ended Termination for SSTL15 inputs with programmable resistor values of 40,
• Common mode termination of 80, 100, 120 ohms for differential inputs
50, or 60 ohms. This is particularly useful for low power JEDEC compliant DDR3 memory controller imple-
mentations. External termination to Vtt should be used for DDR2 memory controller implementation.
LVDS25
BLVDS25
MLVDS
HSTL18_I
HSTL18_II
HSTL18D_I
HSTL18D_II
HSTL15_I
HSTL15D_I
SSTL25_I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL18_II
SSTL18D_I
SSTL18D_II
SSTL15
SSTL15D
1. TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR when turn on can only have
2. External termination to VTT should be used when implementing DDR2 memory controller.
one setting per bank. Only left and right banks have this feature.
Use of TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive
in an I/O bank.
On-chip termination tolerance +/- 20%
Programmable resistance (40, 50 and 60 Ohms)
IO_TYPE
Parallel Single-Ended Input
Off-chip
Vtt
TERMINATE to VTT
On-Chip
Zo
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
+
Control Signal
-
þ
þ
þ
1, 2
2-43
DIFFRENTIAL TERMINATION RESISTOR
Off-chip
*Vtt must be left floating for this termination
On-Chip
80, 100, 120
80, 100, 120
80, 100, 120
Vtt*
Differential Input
LatticeECP3 Family Data Sheet
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
Z0
Z0
+
-
1
Architecture