A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 59
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A3P250-VQG100
Manufacturer Part Number
A3P250-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P250-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250-VQG100
Manufacturer:
NXP
Quantity:
3 400
Part Number:
A3P250-VQG100
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P250-VQG100I
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Drive
Strength
100 µA
100 µA
100 µA
100 µA
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to
operate at the equivalent software default drive strength. These values are for normal ranges ONLY.
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard I/O Banks
Software
Strength
Option
Default
Equiv.
Drive
2 mA
6 mA
8 mA
4 mA
1
Speed
Grade
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
t
DOUT
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
10.93
10.93
9.29
8.16
9.29
8.16
6.82
5.80
5.09
6.82
5.80
5.09
t
DP
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
R e v i s i o n 9
0.04
0.04
0.04
0.03
t
DIN
1.52
1.29
1.13
1.52
1.29
1.13
1.52
1.29
1.13
1.52
1.29
1.13
t
PY
Table 2-6 on page 2-6
t
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
EOUT
10.93
10.93
9.29
8.16
9.29
8.16
6.82
5.80
5.09
6.82
5.80
5.09
t
ZL
9.46
9.46
8.04
7.06
8.04
7.06
5.70
4.85
4.25
5.70
4.85
4.25
for derating values.
t
ZH
ProASIC3 Flash Family FPGAs
3.20
3.20
2.72
2.39
2.72
2.39
3.70
3.15
2.77
3.70
3.15
2.77
t
LZ
3.32
2.82
2.48
3.32
2.82
2.48
4.16
3.54
4.16
3.54
3.11
3.11
t
HZ
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 45