A3P250-VQG100 Actel, A3P250-VQG100 Datasheet - Page 61
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A3P250-VQG100
Manufacturer Part Number
A3P250-VQG100
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P250-VQG100
Processor Series
A3P250
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
157
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P250-VQG100
Manufacturer:
NXP
Quantity:
3 400
Part Number:
A3P250-VQG100
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P250-VQG100I
Manufacturer:
ACTEL
Quantity:
20 000
Company:
Part Number:
A3P250-VQG100T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-56 • Minimum and Maximum DC Input and Output Levels
Table 2-57 • Minimum and Maximum DC Input and Output Levels
2.5 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
2.5 V LVCMOS
Drive Strength
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
larger when operating outside recommended ranges
larger when operating outside recommended ranges
IL
IH
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
Applicable to Advanced I/O Banks
Applicable to Standard Plus I/O Banks
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA
–0.3
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
VIL
VIL
Max.
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
V
Min.
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
V
VIH
VIH
Max.
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
V
Max.
VOL
VOL
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
V
R e v i s i o n 9
VOH
VOH
Min.
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
V
mA mA
I
I
12 12
16 16
24 24
12 12
OL
OL
2
6
2
4
6
8
4
8
I
I
OH
OH
2
6
2
4
6
8
4
8
Max.
I
mA
I
124
OSL
OSL
18
18
37
37
74
18
18
37
37
74
87
3
ProASIC3 Flash Family FPGAs
3
Max., mA
Max.
I
I
mA
169
OSH
OSH
16
16
32
32
65
16
16
32
32
65
83
3
3
µA
µA
I
I
10
10
10
10
10
IL
IL
10
10
10
10
10
10
10
1
1
4
4
µA
µA
I
I
10
10
IH
10
10
10
2- 47
IH
10
10
10
10
10
10
10
2
2
4
4