A3P400-FGG256 Actel, A3P400-FGG256 Datasheet - Page 214
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A3P400-FGG256
Manufacturer Part Number
A3P400-FGG256
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-FGG256
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-FGG256C
Manufacturer:
ACTEL
Quantity:
1 156
Company:
Part Number:
A3P400-FGG256I
Manufacturer:
YAGEO
Quantity:
460 000
Company:
Part Number:
A3P400-FGG256I
Manufacturer:
ACT
Quantity:
1 170
Company:
Part Number:
A3P400-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Datasheet Information
4 - 8
Revision
Advance v0.5
(November 2005)
Advance v0.4
Advance v0.3
M7 device information is new.
The "I/Os Per Package" table was updated.
The "I/Os Per Package" table was updated for the following devices and
packages:
Device
A3P250/M7ACP250
A3P250/M7ACP250
A3P1000
The I/O counts in the "I/Os Per Package" table were updated.
M7 device information is new.
Table 2-4 • ProASIC3 Globals/Spines/Rows by Device was updated to include
the number or rows in each top or bottom spine.
EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options.
The "PLL Macro" section was updated. EXTFB information was removed from
this section.
The CCC Output Peak-to-Peak Period Jitter F
11 • ProASIC3 CCC/PLL Specification
EXTFB was removed from Figure 2-27 • CCC/PLL Macro.
Table 2-13 • ProASIC3 I/O Features was updated.
The "Hot-Swap Support" section was updated.
The "Cold-Sparing Support" section was updated.
"Electrostatic Discharge (ESD) Protection" section was updated.
The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3 Devices was updated.
In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and V
changed to V
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
The "JTAG Pins" section was updated.
"128-Bit AES Decryption" section was updated to include M7 device information.
Table 3-6 was updated.
Table 3-7 was updated.
In Table 3-11, PAC4 was updated.
Table 3-20 was updated.
The note in Table 3-32 was updated.
All Timing Characteristics tables were updated from LVTTL to Register Delays
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
F
TCKMAX
was updated in Table 3-110.
CCI
B1.
R e vi s i o n 9
Changes
Package
VQ100
FG144
FG256
CCC_OUT
was updated in Table 2-
CCI
B2 was
3-31 to 3-
3-85 to
3-93-8
Page
2-24
2-28
2-30
2-33
2-53
3-20
3-27
2-16
2-15
2-29
2-34
2-35
2-64
2-97
2-50
2-51
3-90
3-97
N/A
N/A
3-6
3-6
73
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