MMA8453QR1 Freescale Semiconductor, MMA8453QR1 Datasheet - Page 41
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MMA8453QR1
Manufacturer Part Number
MMA8453QR1
Description
Board Mount Accelerometers LOW G 3-AXIS DGTL ACCEL
Manufacturer
Freescale Semiconductor
Specifications of MMA8453QR1
Sensing Axis
X, Y, Z
Acceleration
2 g, 4 g, 8 g
Digital Output - Number Of Bits
8 bit, 10 bit
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.95 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Digital Output - Bus Interface
I2C
Shutdown
Yes
Sensitivity
256 count/g, 512 count/g, 1024 count/g
Package / Case
QFN-16
Output Type
Digital
Rohs Compliant
YES
Peak Reflow Compatible (260 C)
Yes
Acceleration Range
± 2g, ± 4g, ± 8g
No. Of Axes
3
Ic Interface Type
I2C
Sensor Case Style
QFN
No. Of Pins
16
Supply Voltage Range
1.95V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMA8453QR1
Manufacturer:
FREESCALE
Quantity:
12 000
Part Number:
MMA8453QR1
Manufacturer:
FREESCALE
Quantity:
20 000
Table 53. CTRL_REG1 Description
6.7
Note: Except for STANDBY mode selection, the device must be in STANDBY mode to change any of the fields within
CTRL_REG1 (0x2A).
0x2A: CTRL_REG1 System Control 1 Register
functional blocks are overridden by the data rate set by the ASLP_RATE field.
DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples. The default value is 000 for a data rate of 800 Hz.
ACTIVE bit selects between STANDBY mode and ACTIVE mode. The default value is 0 for STANDBY mode.
LNoise bit selects between normal full dynamic range mode and a high sensitivity, Low Noise mode. In Low Noise mode the
maximum signal that can be measured is ±4g. Note: Any thresholds set above 4g will not be reached.
F_Read bit selects between Normal and Fast Read mode. When selected, the auto increment counter will skip over the LSB data
bytes.
Sensors
Freescale Semiconductor
0x2A CTRL_REG1 Register (Read/Write)
ASLP_RATE1
It is important to note that when the device is Auto-SLEEP mode, the system ODR and the data rate for all the system
ASLP_RATE[1:0]
Bit 7
F_READ
LNOISE
ACTIVE
DR[2:0]
Control Registers
ASLP_RATE0
Table 55. System Output Data Rate Selection
Bit 6
DR2
Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode. Default value: 00.
See
Data rate selection. Default value: 000.
See
Reduced noise reduced Maximum range mode. Default value: 0.
(0: Normal mode; 1: Reduced Noise mode)
Fast Read mode: Data format limited to single Byte Default value: 0.
(0: Normal mode 1: Fast Read Mode)
Full Scale selection. Default value: 00.
(0: STANDBY mode; 1: ACTIVE mode)
0
0
0
0
1
1
1
1
Table 54
Table 55
Table 54. SLEEP Mode Rate Description
Bit 5
ASLP_RATE1
DR2
for more information.
for more information.
Table 56. Full Scale Selection
DR1
0
0
1
1
0
0
1
1
0
0
1
1
Active
0
1
Bit 4
DR1
ASLP_RATE0
DR0
0
1
0
1
0
1
0
1
0
1
0
1
STANDBY
ACTIVE
Mode
Bit 3
DR0
Frequency (Hz)
12.5 Hz
6.25 Hz
1.56 Hz
800 Hz
400 Hz
200 Hz
100 Hz
50 Hz
ODR
12.5
6.25
1.56
50
LNOISE
Bit 2
1.25 ms
160 ms
640 ms
Period
2.5 ms
10 ms
20 ms
80 ms
5 ms
F_READ
Bit 1
MMA8453Q
ACTIVE
Bit 0
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