LIS35DE STMicroelectronics, LIS35DE Datasheet
LIS35DE
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LIS35DE Summary of contents
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... Motion activated functions ■ Gaming and virtual reality input devices ■ Vibration monitoring and compensation Description The LIS35DE is an ultra compact low-power three axis linear accelerometer. It includes a sensing element and an IC interface able to provide the measured acceleration to the external world 2 through I C/SPI serial interface ...
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... SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 5.2.2 5.2.3 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/39 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C - Inter IC Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Click and double click recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 15594 Rev 1 LIS35DE ...
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... LIS35DE 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 CTRL_REG1 (20h 7.2 CTRL_REG2 (21h 7.3 CTRL_REG3 [interrupt CTRL register] (22h 7.4 HP_FILTER_RESET (23h 7.5 STATUS_REG (27h 7.6 OUT_X (29h 7.7 OUT_Y (2Bh 7.8 OUT_Z (2Dh 7.9 FF_WU_CFG_1 (30h 7.10 FF_WU_SRC_1 (31h 7.11 FF_WU_THS_1 (32h 7.12 FF_WU_DURATION_1 (33h ...
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... FF_WU_SRC_2 (35h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 42. FF_WU_THS_2 (36h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 43. FF_WU_THS_2 (36h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 44. FF_WU_DURATION_2 (37h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 45. FF_WU_DURATION_2 (37h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 46. CLICK_CFG (38h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 47. CLICK_CFG (38h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 48. Click interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 49. CLICK_SRC (39h) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4/39 Doc ID 15594 Rev 1 LIS35DE ...
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... LIS35DE Table 50. CLICK_SRC (39h) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 51. CLICK_THSY_X (3Bh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 52. CLICK_THSY_X (3Bh) register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 53. CLICK_THSZ (3Ch) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 54. CLICK_THSZ (3Ch) register description Table 55. CLICK_TimeLimit (3Dh) register Table 56. CLICK_Latency (3Eh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 57. CLICK_Window (3Fh) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 15594 Rev 1 ...
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... Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. I2C Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. LIS35DE electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Multiple bytes SPI Read protocol (2 bytes example Figure 9. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10 ...
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... LIS35DE 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram REFERENCE 1.2 Pin description Figure 2. Pin connection Y 6 CHARGE AMPLIFIER A/D MUX CONVERTER TRIMMING CLOCK CIRCUITS TOP VIEW Doc ID 15594 Rev 1 Block diagram and pin description CS SCL/SPC CONTROL LOGIC ...
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... C less significant bit of the device address 2 SDA I C serial data (SDA) SDI SPI serial data input (SDI) SDO 3-wire interface serial data output (SDO) 2 SCL I C serial clock (SCL) SPC SPI serial port clock (SPC) Doc ID 15594 Rev 1 LIS35DE Function 2 C mode; 0: SPI enabled) ...
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... LIS35DE 2 Mechanical and electrical specifications 2.1 Mechanical characteristics T = 25°C unless otherwise noted Table 3. Mechanical characteristics @ Vdd=2.5 V Symbol Parameter FS Measurement range Dres Device resolution So Sensitivity Sensitivity change vs TCSO temperature Typical zero-g level offset TyOff (4) accuracy Zero-g level change vs TCOff temperature (5) BW ...
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... It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the measurement chain is powered off. 4. Filter cut-off frequency. 5. Time to obtain valid data after exiting power-down mode. 10/39 (1) Test conditions ( 25°C, ODR=100 25°C DR=0 DR=1 Doc ID 15594 Rev 1 LIS35DE (2) Min. Typ. Max. 2.16 2.5 3.6 1.71 Vdd+0.1 0.3 0. ...
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... LIS35DE 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values Symbol tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) CS hold time tsu(SI) SDI input setup time ...
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... Doc ID 15594 Rev 1 ( fast mode Min Max 0 400 1.3 0.6 100 0.01 0.9 (2) 300 20 + 0.1C b (2) 300 20 + 0.1C b 0.6 0.6 0.6 1.3 REPEATED t su(SR) t w(SP:SR) t su(SP) LIS35DE Unit KHz µs ns µs ns µs START START STOP ...
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... LIS35DE 2.4 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... INT2). A more advanced feature allows to generate and interrupt request when a “double click” with programmable time between the two events enabling a “mouse button like” use. This function can be fully programmed by the user in terms of expected amplitude and timing of the stimuli. 14/39 Doc ID 15594 Rev 1 LIS35DE ...
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... The acceleration data may be accessed through an I device particularly suitable for direct interfacing with a microcontroller. The LIS35DE features a Data-Ready signal (RDY) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. ...
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... Application hints 4 Application hints Figure 5. LIS35DE electrical connection Vdd 10uF 100nF GND The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF Al) should be placed as near as possible to the pin 6 of the device (common design practice). ...
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... Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines are connected to Vdd_IO through a pull-up resistor embedded inside the LIS35DE. When the bus is free both the lines are high. 2 ...
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... If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS35DE is 001110xb. SDO pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ ...
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... In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge. 5.2 SPI bus interface The LIS35DE SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO. SAD + W ...
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... The function and the behavior of SDI and SDO remain unchanged. 20/ AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Doc ID 15594 Rev 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 LIS35DE ...
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... LIS35DE 5.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI SDO The SPI read command is performed with 16 clock pulses. Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0 do not increment address, when 1 increment address in multiple reading ...
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... DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 AD5 AD4 AD3 AD2 AD1 AD0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 Doc ID 15594 Rev 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 LIS35DE ...
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... LIS35DE 6 Register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related address: Table 16. Register address map Name Reserved (do not modify) Ctrl_Reg1 Ctrl_Reg2 Ctrl_Reg3 HP_filter_reset Reserved (do not modify) Status_Reg -- OutX -- OutY -- OutZ Reserved (do not modify) ...
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... The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up. 24/39 Register address Type Hex Binary rw 3E 011 1110 00000000 rw 3F 011 1111 00000000 Doc ID 15594 Rev 1 LIS35DE Default Comment ...
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... LIS35DE 7 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 CTRL_REG1 (20h) Table 17. CTRL_REG1 (20h) register ...
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... FDS bit enables (FDS=1) or bypass (FDS=0) the high pass filter in the signal chain of the sensor HP_coeff[2:1]. These bits are used to configure high-pass filter cut-off frequency ft. Table 21. High pass filter cut-off frequency configuration HP_coeff2 26/39 HP_FF_ -- FDS WU2 ft (Hz) (DR=100 Hz Doc ID 15594 Rev 1 LIS35DE HP_FF_ HP_coeff2 HP_coeff1 WU1 ft (Hz) (DR=400 Hz ...
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... LIS35DE Table 21. High pass filter cut-off frequency configuration (continued) HP_coeff2 7.3 CTRL_REG3 [interrupt CTRL register] (22h) Table 22. CTRL_REG3 [interrupt CTRL register] (22h) register IHL PP_OD Table 23. CTRL_REG3 [interrupt CTRL register] (22h) register description IHL Interrupt active high, low. Default value 0. (0: active high; 1: active low) PP_OD Push-pull/Open Drain selection on interrupt pad ...
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... Table 27. OUT_X (29h) register XD7 XD_6 X axis output data. 7.7 OUT_Y (2Bh) Table 28. OUT_Y (2Bh) register YD7 YD6 28/39 YOR XOR ZYXDA XD5 XD4 XD3 YD5 YD4 YD3 Doc ID 15594 Rev 1 LIS35DE ZDA YDA XDA XD2 XD1 XD0 YD2 YD1 YD0 ...
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... LIS35DE Y axis output data. 7.8 OUT_Z (2Dh) Table 29. OUT_Z (2Dh) register ZD7 ZD6 Z axis output data. 7.9 FF_WU_CFG_1 (30h) Table 30. FF_WU_CFG_1 (30h) register AOI LIR Table 31. FF_WU_CFG_1 (30h) register description And/Or combination of Interrupt events. Default value: 0 AOI (0: OR combination of interrupt events; 1: AND combination of interrupt events) Latch Interrupt request into FF_WU_SRC reg with the FF_WU_SRC reg cleared by reading FF_WU_SRC_1 reg ...
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... If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented. 30/ THS5 THS4 Resetting mode selection. Default value: 0 (0: counter resetted; 1: counter decremented) Free-fall / wake-up Threshold: default value: 000 0100 Doc ID 15594 Rev THS3 THS2 THS1 LIS35DE XL THS0 ...
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... LIS35DE 7.12 FF_WU_DURATION_1 (33h) Table 36. FF_WU_DURATION_1 (33h) register D7 D6 Table 37. FF_WU_DURATION_1 (33h) register description Duration register for Free-Fall/Wake-Up interrupt 1. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from 0 to 2.55 sec when ODR=100Hz. The counter used to implement duration function is blocked when LIR=1 in configuration register and the interrupt event is verified 7 ...
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... Free-fall / wake-up Threshold. Default value: 000 0000 Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration counter is decremented. 32/ THS5 THS4 THS3 Doc ID 15594 Rev 1 LIS35DE THS2 THS1 THS0 ...
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... LIS35DE 7.16 FF_WU_DURATION_2 (37h) Table 44. FF_WU_DURATION_2 (37h) register D7 D6 Table 45. FF_WU_DURATION_2 (37h) register description Duration value. Default value: 0000 0000 Duration register for Free-Fall/Wake-Up interrupt 2. Duration step and maximum value depend on the ODR chosen. Step 2.5 msec, from 0 to 637.5 msec if ODR=400Hz, else step 10 msec, from ...
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... Enable interrupt generation on single click event on X axis. Default value: 0 Single_X (0: disable interrupt request; 1: enable interrupt request) Table 48. Click interrupt configurations Double_Z / 34/39 Double_Z Single_Z Double_Y Single_Z / Doc ID 15594 Rev 1 LIS35DE Single_Y Double_X Single_X Click output 0 Single Double Single OR Double ...
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... LIS35DE 7.18 CLICK_SRC (39h) Table 49. CLICK_SRC (39h) register X IA Table 50. CLICK_SRC (39h) register description Interrupt Active. Default value (0: no interrupt has been generated; 1: one or more interrupt event has been generated) Double click on Z axis event. Default value: 0 Double_Z (0: no interrupt; 1: Double Z event has occurred) Single click on Z axis event ...
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... CLICK_Window (3Fh) register Win7 Win6 From 0 to 255 msec with step of 1 msec. 36/39 Click Threshold on Z axis. Default value: 0000 Dur5 Dur4 Lat5 Lat4 Win5 Win4 Doc ID 15594 Rev 1 Dur3 Dur2 Dur1 Lat3 Lat2 Lat1 Win3 Win2 Win1 LIS35DE Dur0 Lat0 Win0 ...
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... LIS35DE 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. Figure 12. LGA14: mechanical data and package dimensions DIM. MIN. ...
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... Revision history 9 Revision history Table 58. Document revision history Date 29-Apr-2009 38/39 Revision 1 Initial release Doc ID 15594 Rev 1 LIS35DE Changes ...
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... LIS35DE Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...