ICS9P936AFLF IDT, Integrated Device Technology Inc, ICS9P936AFLF Datasheet - Page 2

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ICS9P936AFLF

Manufacturer Part Number
ICS9P936AFLF
Description
IC FANOUT/BUFF DDR I/II 28TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of ICS9P936AFLF

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Pin Description
IDT
PIN #
ICS9P936
Low Skew Dual Bank DDR I/II Fan-out Buffer
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
TM
/ICS
TM
PIN NAME
AVDD2.5
AGND
BUF_INT
BUF_INC
DDRT0
DDRC0
DDRT1
DDRC1
GND
VDDQ2.5/1.8
FB_OUTT
FB_OUTC
DDRT2
DDRC2
SCLK
SDATA
DDRC3
DDRT3
DDRC4
DDRT4
VDDQ2.5/1.8
GND
DDRC5
DDRT5
AGND
AVDD2.5
VDDQ2.5/1.8
GND
Low Skew Dual Bank DDR I/II Fan-out Buffer
PIN TYPE
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
PWR
PWR
I/O
IN
IN
IN
Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively
Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
True Buffer In signal for memory outputs.
Complementary Buffer In signal for memory outputs.
-40
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V or 1.8V for DDR or DDR 2 outputs respectively
True single-ended feedback output, dedicated external feedback. It switches
at the same frequency as other DDR outputs.
Complementary single-ended feedback output, dedicated external feedback.
It switches at the same frequency as other DDR outputs.
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Analog Ground pin for Core PLL
2.5V Analog Power pin for Core PLL
Ground pin.
2
1084C 12/03/09

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