SI5020-B-GM Silicon Laboratories Inc, SI5020-B-GM Datasheet
SI5020-B-GM
Specifications of SI5020-B-GM
Related parts for SI5020-B-GM
SI5020-B-GM Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5020 represents a new standard in low jitter, low power, and small size for high-speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (– °C). ...
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... Si5020 2 Rev. 1.5 ...
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... Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8. Package Outline: Si5010-BM/ 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Rev. 1.5 Si5020 Page 3 ...
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... Si5020 1. Detailed Block Diagram DIN+ DIN+ Phase Phase Phase Detector Detector Detector DIN– REFCLK+ REFCLK+ REFCLK– 2 RATESEL1-0 RATESEL1-0 REXT Bias Bias Bias G eneration G eneration G eneration 4 CLK A/D VCO DSP Divider n Lock Detector Calibration Rev. 1.5 DOUT+ Retim e Retim e Retim e DOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5020 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "Typical Application Schematic" on page 10. ...
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... Si5020 Table 2. DC Characteristics (V = 2.5 V ±5 – ° Parameter Supply Current OC-48 and FEC (2.7 GHz) GbE OC-12 OC-3 Power Dissipation OC-48 and FEC (2.7 GHz) GbE OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK)* Single-Ended Input Voltage (DIN, REFCLK)* Differential Input Voltage Swing ...
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... TOL(PP 300 6.5 kHz kHz T IEEE 802.3z Clause 38.68 JT(PP) D IEEE 802.3z Clause 38.69 JT(PP) J with no jitter on serial data GEN(rms) J with no jitter on serial data GEN(PP) Rev. 1.5 Si5020 Min Typ Max Unit .15 — 2.7 GHz — 80 110 ps 225 250 270 ps 225 ...
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... Si5020 Table 4. AC Characteristics (PLL Characteristics) (Continued) (V 2.5 V ±5 – ° Parameter * Jitter Transfer Bandwidth * Jitter Transfer Peaking Acquisition Time Input Reference Clock Duty Cycle Reference Clock Range Input Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock ...
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... Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol Value V –0 –0.3 to 3.6 DIG V –0 0.3) DIF DD ±50 T –55 to 150 JCT T –55 to 150 STG 1 Symbol Test Condition ϕ Still Air JA Rev. 1.5 Si5020 Unit °C °C kV Value Unit 38 °C/W 9 ...
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... Si5020 3. Typical Application Schematic DIN+ High-Speed Serial Input DIN– System REFCLK+ Reference REFCLK– Clock 10 LVTTL Control Inputs Loss-of-Lock Indicator 2 DOUT+ DOUT– Si5020 CLKOUT+ CLKOUT– 0.1 μF VDD 10 kΩ 2200 Rev. 1.5 Recovered Data Recovered Clock ...
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... REFCLK, indicating the frequency lock status of the PLL is unknown. Additionally, the Si5020 uses the reference clock to center the VCO output frequency so that clock and data can be recovered from the input data stream. The device self configures for operation with one of three reference clock frequencies ...
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... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 2, December 1995 and ITU-T G.958. 4.7.1. Jitter Tolerance The Si5020’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 4. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device ...
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... DSPLL, and will begin to lock to the data stream. 4.9. Device Grounding The Si5020 uses the GND pad on the bottom of the 20- 20 dB/Dec ade pin micro leaded package (MLP) for device ground. This Slope pad should be connected directly to the analog supply ground ...
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... Si5020 VDD 2.5 kΩ 0.1 μ Ω REFCLK + 10 kΩ 2.5 kΩ 100 Ω REFCLK – 0.1 μF GND Si5020 VDD 2.5 kΩ 0.1 μ Ω DIN + 10 kΩ 2.5 kΩ 100 Ω DIN – 0.1 μF GND Rev. 1.5 102 Ω ...
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... Differential Output Circuitry The Si5020 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 μF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6 ...
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... VDD Figure 10. Si5020 Pin Configuration Table 9. Si5020 Pin Descriptions I/O Signal Level External Bias Resistor. This resistor is used by onboard circuitry to estab- lish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resis- tor. Differential Reference Clock. ...
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... Table 9. Si5020 Pin Descriptions (Continued) Pin # Pin Name 15 PWRDN/CAL 16 CLKOUT– 17 CLKOUT+ 19 RATESEL0 20 RATESEL1 2, 7, 11, 14 VDD 3, 8, 18, and GND GND Pad I/O Signal Level I LVTTL Powerdown. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low ...
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... Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Silicon Labs Part Number Si5020-B-GM 18 Voltage Pb-Free 2.5 Yes ...
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... Package Outline Figure 11 illustrates the package details for the Si5020. Table 10 lists the values for the dimensions shown in the illustration. Figure 11. 20-pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 c — — D 4.00 BSC D2 1.95 2 ...
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... Si5020 9. 4x4 mm 20L QFN Recommended PCB Layout See Note 8 Symbol A Pad Row/Column Width/Length D Thermal Pad Width/Height e Pad Pitch G Pad Row/Column Separation R Pad Radius X Pad Width Y Pad Length Z Pad Row/Column Extents Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad ...
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... Added "4x4 mm 20L QFN Recommended PCB Layout" on page 20. Revision 1.3 to Revision 1.4 Made minor note corrections to "4x4 mm 20L QFN Recommended PCB Layout" on page 20. Revision 1.4 to Revision 1.5 Added "Top Mark" on page 18. Updated "Ordering Guide" on page 18. Updated "Package Outline" on page 19. Rev. 1.5 Si5020 21 ...
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... Si5020 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...