SI5020-B-GM Silicon Laboratories Inc, SI5020-B-GM Datasheet - Page 13

• Manufacturer Part Number: SI5020-B-GM
• Description: IC CLK DATA REC SONET/SDH 20-QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5020-B-GM

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.8. Powerdown
The Si5020 provides a powerdown pin, PWRDN/CAL,
that disables the output drivers (DOUT, CLKOUT).
When the PWRDN/CAL pin is driven high, the positive
and negative terminals of CLKOUT and DOUT are each
tied to VDD through 100 Ω on-chip resistors. This
feature is useful in reducing power consumption in
applications that employ redundant serial channels.
Trans f er
Jitter
0.1 dB
Figure 5. Jitter Transfer Specification
Dif f erential Driv er
A c c eptable
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
Range
SONET
Data Rate
OC-48
OC-12
OC-3
Frequenc y
Fc
Fc
(k Hz )
2000
500
130
0.1
0.1
20 dB/Dec ade
μ
μ
F
F
Slope
Z o = 50
Z o = 50
Ω
Ω
Rev. 1.5
R F C LK +
R F C LK –
When PWRDN/CAL is released (set to low) the digital
logic resets to a known initial condition, recalibrates the
DSPLL, and will begin to lock to the data stream.
4.9. Device Grounding
The Si5020 uses the GND pad on the bottom of the 20-
pin micro leaded package (MLP) for device ground. This
pad should be connected directly to the analog supply
ground. See Figures 10 and 11 for the ground (GND)
pad location.
4.10. Bias Generation Circuitry
The Si5020 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents, which significantly
reduces
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
4.11. Differential Input Circuitry
The Si5020 provides differential inputs for both the high-
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 6. In applications where direct dc
coupling is possible, the 0.1 μF capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
voltage listed in Table 2 on page 6.
2.5 k
10 k
Si5020
Ω
Ω
power
V DD
GND
2.5 k
10 k
Ω
Ω
consumption
102
Ω
versus
Si5020
traditional
13