PT7C4311WEX Pericom Semiconductor, PT7C4311WEX Datasheet - Page 10

• Manufacturer Part Number: PT7C4311WEX
• Description: IC REAL TIME CLK/CALENDAR 8-SOIC
• Manufacturer: Pericom Semiconductor
• Type: Clock/Calendarr

Specifications of PT7C4311WEX

• Memory Size: 56B
• Time Format: Binary
• Date Format: Binary
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PT7C4311WEXTR

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When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.
After transmitting the ACK signal, if the Master remains the receiver for transfer of the next byte, the SDA is released at the
falling edge of the clock corresponding to the 9th bit of data on the SCL line. Data transfer resumes when the Master becomes the
transmitter.
When the Master is the receiver, if the Master does not send an ACK signal in response to the last byte sent from the slave, that
indicates to the transmitter that data transfer has ended. At that point, the transmitter continues to release the SDA and awaits a
STOP condition from the Master.
e)
The I
slave addresses are allocated to each device.
All communications begin with transmitting the [START condition] + [slave address (+ R/W specification)]. The receiving device
responds to this communication only when the specified slave address it has received matches its own slave address.
Slave addresses have a fixed length of 7 bits. See table for the details.
An R/W bit is added to each 7-bit slave address during 8-bit transfers.
2. I
PT0322(08/09)
Operation
Data acknowledge response (ACK signal)
Slave Address
2
Write
C bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a chip select pin,
Read
2
C Bus’s Basic Transfer Format
SDA from transmitter
SCL from Master
SDA from receiver
(sending side)
(receiving side)
Transfer data
Sr
D1 h
D0 h
S
Start indication
Restart indication
1
bit 7
1
bit 6
1
2
P
bit 5
Stop indication
0
Slave address
10
bit 4
1
bit 3
A
A
0
Real-time Clock Module (I
RTC Acknowledge
Master Acknowledge
8
bit 2
0
bit 1
0
Release SDA
ACK signal
Low active
9
0 (= Write)
1 (= Read)
Data Sheet
R / W bit
PT7C4311
bit 0
2
C Bus)
Ver: 2