MSC7116VF1000 Freescale Semiconductor, MSC7116VF1000 Datasheet - Page 37

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MSC7116VF1000

Manufacturer Part Number
MSC7116VF1000
Description
DSP 16BIT W/DDR CTRLR 400-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MSC711x StarCorer
Type
Fixed Pointr
Datasheet

Specifications of MSC7116VF1000

Interface
Host Interface, I²C, UART
Clock Rate
266MHz
Non-volatile Memory
ROM (8 kB)
On-chip Ram
400kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 105°C
Mounting Type
*
Package / Case
400-MAPBGA
Device Core Size
16b
Format
Fixed Point
Clock Freq (max)
266MHz
Mips
266
Device Input Clock Speed
266MHz
Ram Size
192KB
Program Memory Size
Not RequiredKB
Operating Supply Voltage (typ)
1.2/2.5/3.3V
Operating Supply Voltage (min)
1.14/2.38/3.14V
Operating Supply Voltage (max)
1.26/2.63/3.47V
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
400
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MSC7116VF1000
Manufacturer:
SONY
Quantity:
6 218
Part Number:
MSC7116VF1000
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
2.5.9
2.5.10
Figure 24 shows the signal behavior of the
Freescale Semiconductor
Notes:
No.
400
401
402
Number
65
66
Internal bus clock (APBCLK)
Internal bus clock period (1/APBCLK)
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
1.
2.
3.
UART Timing
EE Timing
The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details.
Refer to Table 1-11 on page 1-16 for details on EE pin functionality.
UTXD, URXD
UTXD Output
EE0 input to the core
EE0 output from the core
inputs
Characteristics
Characteristics
EE0 Out
EE0 In
EE
Figure 22. UART Output Timing
Figure 21. UART Input Timing
MSC7116 Data Sheet, Rev. 13
pin.
401
402
Figure 23. EE Pin Timing
Table 27. UART Timing
Table 28. EE0 Timing
400
Synchronous to core clock
Asynchronous
Type
Expression
16 × T
F
T
CORE
APBCLK
APBCLK
402
/2
66
65
401
400
120.3
Min
7.52
4 core clock periods
1 core clock period
Max
133
5
5
Min
Unit
MHz
ns
ns
ns
ns
37

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