XC3S50AN-4FTG256I Xilinx Inc, XC3S50AN-4FTG256I Datasheet - Page 59

• Manufacturer Part Number: XC3S50AN-4FTG256I
• Description: IC FPGA SPARTAN-3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S50AN-4FTG256I

• Number Of Logic Elements/cells: 1584
• Number Of Labs/clbs: 176
• Total Ram Bits: 55296
• Number Of I /o: 195
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Suspend Mode Timing
X-Ref Target - Figure 12
Table 49: Suspend Mode Timing Parameters
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
Entering Suspend Mode
T
T
T
T
T
Exiting Suspend Mode
T
T
T
T
T
T
AWAKE_GWE1
AWAKE_GWE512
AWAKE_GTS1
AWAKE_GTS512
SUSPENDHIGH_AWAKE
SUSPENDFILTER
SUSPEND_GTS
SUSPEND_GWE
SUSPEND_DISABLE
SUSPENDLOW_AWAKE
SUSPEND_ENABLE
These parameters based on characterization.
For information on using the Spartan-3AN Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
Flip-Flops, Block RAM,
Symbol
SUSPEND Input
AWAKE Output
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled
(suspend_filter:Yes)
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
Falling edge of the SUSPEND pin to rising edge of the AWAKE pin
Does not include DCM lock time
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512
Entering Suspend Mode
Figure 12: Suspend Mode Timing
t
SUSPEND_GWE
t
SUSPENDHIGH_AWAKE
t
SUSPEND_GTS
Description
www.xilinx.com
Defined by SUSPEND constraint
Spartan-3AN FPGA Family: DC and Switching Characteristics
t
SUSPEND_DISABLE
Exiting Suspend Mode
Blocked
Write Protected
t
SUSPEND_ENABLE
t
sw_gts_cycle
SUSPENDLOW_AWAKE
sw_gwe_cycle
+160
Min
–
–
–
–
–
–
–
–
–
–
t
3.7 to 109
AWAKE_GTS
4 to 108
+300
Typ
340
< 5
10
67
14
57
14
7
t
DS610-3_08_061207
AWAKE_GWE
+600
Max Units
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
µs
µs
ns
µs
ns
µs
59