XC3S1400AN-4FGG484I Xilinx Inc, XC3S1400AN-4FGG484I Datasheet - Page 30

• Manufacturer Part Number: XC3S1400AN-4FGG484I
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484I

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Read Commands
Fast Read
Table 3-2: Fast Read (0x0B) Command Summary
30
MOSI
MISO
Notes:
1. The Fast Read command Is supported in simulation.
Pin
Command
Byte 1
0x0B
Default Addressing: See
Optional Power-of-2 Addressing: See
Table A-3, page 89
High Address Middle Address Low Address
Byte 2
24-bit Starting Page and Byte Address
The Fast Read command is best for longer, sequential read operations. This is the same
command that the FPGA issues during configuration. This command is also best for code
shadowing applications, where the FPGA application copies a large amount of code or
data into external SRAM or DDR SDRAM for a MicroBlaze™ processor. Although it has
longer initial latency than the Random Read command, the Fast Read command supports
a CLK clock frequency up to 50 MHz.
The Fast Read command sequentially reads a continuous stream of data directly from
Flash memory bypassing the SRAM page buffers, as shown in
specifies an initial starting byte address in the ISF memory. The ISF memory incorporates
an internal address pointer that automatically increments on every clock cycle, allowing
one continuous read operation without requiring additional address sequences.
To perform a Fast Read command, summarized in
Figure
•
•
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the Fast Read command code, 0x0B,
most-significant bit first.
3-2, the FPGA application must perform the following actions.
MOSI
MISO
Random Read
CSB
CLK
Fast Read
Byte 3
High
Figure 3-1: Fast Read and Random Read Commands
SPI_ACCESS
Table 2-2, page 19
(0x0B): 50 MHz maximum
(0x03): 33 MHz maximum
www.xilinx.com
Byte 4
Don’t Care
Spartan-3AN FPGA In-System Flash User Guide
Byte 5
Byte
XX
Automatically increments through
memory, crossing page
boundaries
Table 2-2, page 19
Flash Memory Array
Data Byte +0
Byte 6
(most-significant bit first)
Starting byte address
XX
ISF Memory Data Bytes
UG333 (v2.1) January 15, 2009
Figure
and shown in detail in
UG333_c3_03_021307
3-1. The command
...
...
...
Data Byte +n
Byte n+6
XX
R