LPC11C22FBD48/301, NXP Semiconductors, LPC11C22FBD48/301, Datasheet - Page 27
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LPC11C22FBD48/301,
Manufacturer Part Number
LPC11C22FBD48/301,
Description
TXRX CORTEX CAN 16K FLASH
Manufacturer
NXP Semiconductors
Series
LPC11Cxxr
Datasheet
1.LPC11C14FBD48301.pdf
(61 pages)
Specifications of LPC11C22FBD48/301,
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CAN Transceiver, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
36
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-6643
LPC11C22FBD48/301
LPC11C22FBD48/301
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC11C22FBD48/301,
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
LPC11CX2_CX4
Product data sheet
7.17.6 APB interface
7.17.7 AHBLite
7.17.8 External interrupt inputs
7.18 Emulation and debugging
The C_CAN ISP command handler uses the CANopen protocol and data organization
method. C_CAN ISP commands have the same functionality as UART ISP commands.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 3 December 2010
Section
7.17.1).
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2010. All rights reserved.
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