PIC18LF26K80-I/SS Microchip Technology, PIC18LF26K80-I/SS Datasheet - Page 364
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PIC18LF26K80-I/SS
Manufacturer Part Number
PIC18LF26K80-I/SS
Description
MCU PIC 64KB FLASH 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18LF26K80-I/SS
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.200", 5.30mm Width)
Controller Family/series
PIC18
Ram Memory Size
4KB
Cpu Speed
16MIPS
No. Of Pwm Channels
5
Processor Series
PIC18LF26K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F66K80 FAMILY
23.2
23.2.1
REGISTER 23-1:
DS39977C-page 364
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-2
bit 1
bit 0
Note 1:
U-0
—
2:
3:
A/D Registers
These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return random values.
Channel 28 turns off analog MUX switches to allow for minimum capacitive loading of the ADC input, for
finer resolution CTMU time measurements.
A/D CONTROL REGISTERS
Unimplemented: Read as ‘ 0 ’
CHS<4:0>: Analog Channel Select bits
00000 = Channel 00 (AN0)
00001 = Channel 01 (AN1)
00010 = Channel 02 (AN2)
00011 = Channel 03 (AN3)
00100 = Channel 04 (AN4)
00101 = Channel 05 (AN5)
00110 = Channel 06 (AN6)
00111 = Channel 07 (AN7)
01000 = Channel 08 (AN8)
01001 = Channel 09 (AN9)
01010 = Channel 10 (AN10)
01011 = (Reserved)
01100 = (Reserved)
01101 = (Reserved)
01110 = (Reserved)
01111 = (Reserved)
GO/DONE: A/D Conversion Status bit
1 = A/D cycle is in progress. Setting this bit starts an A/D conversion cycle. The bit is cleared
0 = A/D conversion has completed or is not in progress
ADON: A/D On bit
1 = A/D Converter is operating
0 = A/D conversion module is shut off and consuming no operating current
R/W-0
CHS4
automatically by hardware when the A/D conversion is completed.
ADCON0: A/D CONTROL REGISTER 0
W = Writable bit
‘1’ = Bit is set
R/W-0
CHS3
(2)
(2))
(2))
(2))
(2)
(1,2)
(1,2)
(1,2)
R/W-0
CHS2
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
10000 = (Reserved)
10001 = (Reserved)
10010 = (Reserved)
10011 = (Reserved)
10100 = (Reserved)
10101 = (Reserved)
10110 = (Reserved)
10111 = (Reserved)
11000 = (Reserved)
11001 = (Reserved)
11010 = (Reserved)
11011 = (Reserved)
11100 = (MUX disconnect)
11101 = Channel 29 (temperature diode)
11110 = Channel 30 (V
11111 = Channel 31 (1.024V band gap)
R/W-0
CHS1
R/W-0
CHS0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
DDCORE
2011 Microchip Technology Inc.
(3)
x = Bit is unknown
GO/DONE
)
R/W-0
R/W-0
ADON
bit 0
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