STM32F101T6U6ATR STMicroelectronics, STM32F101T6U6ATR Datasheet - Page 61

• Manufacturer Part Number: STM32F101T6U6ATR
• Description: IC ARM CORTEX MCU 32KB 36VFQFPN
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F101T6U6ATR

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 36MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 36-VFQFN Exposed Pad
• Core: ARM Cortex M3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STM32F101x4, STM32F101x6
SPI interface characteristics
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
Refer to
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 41.
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
su(NSS)
t
a(SO)
Symbol
1/t
t
t
t
t
t
t
h(NSS)
su(MI)
v(SO)
t
v(MO)
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
SCK
c(SCK)
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Section 5.3.12: I/O current injection characteristics
(1)
(1)
(1)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Master mode
Data input setup time
Slave mode
Data input hold time
Master mode
Data input hold time
Slave mode
Data output access time
Data output disable time Slave mode
Data output valid time
Data output valid time
Data output hold time
Parameter
Table
Doc ID 15058 Rev 5
8.
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Master mode, f
presc = 4
SPI
SPI
Slave mode, f
presc = 4
Slave mode, f
Slave mode (after enable edge)
Master mode (after enable
edge)
Slave mode (after enable edge)
Master mode (after enable
edge)
PCLKx
Conditions
PCLK
PCLK
frequency and V
PCLK
Table 41
= 24 MHz
= 36 MHz,
= 36 MHz,
for more details on the
are derived from tests
Electrical characteristics
DD
4 t
Min
73
10
PCLK
supply voltage
50
25
0
1
1
1
4
0
3
0
0
4 t
Max
25
18
60
55
18
PCLK
8
3
MHz
Unit
61/79
ns