MC56F8246VLF Freescale Semiconductor, MC56F8246VLF Datasheet - Page 8

DSC 48K FLASH 60MHZ 48-LQFP

MC56F8246VLF

Manufacturer Part Number
MC56F8246VLF
Description
DSC 48K FLASH 60MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8246VLF

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
3K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
39
Data Ram Size
6 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 5 Channel
Package
48LQFP
Family Name
MC56F82xx
Maximum Speed
60 MHz
Data Bus Width
16 Bit
Interface Type
I2C/SCI/SPI
On-chip Dac
1-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number
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Quantity
Price
Part Number:
MC56F8246VLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC56F8246VLF
Manufacturer:
FREESCALE
Quantity:
20 000
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Part Number:
MC56F8246VLF
Quantity:
42
Overview
2.1.6
2.2
Processor Expert (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software
application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment (IDE) is a sophisticated tool for code navigation, compiling, and
debugging. A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards supports
concurrent engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and
efficient development.
2.3
The MC56F825x/MC56F824x’s architecture appears in
buses communicate with internal memories and the IP bus interface as well as the internal connections among the units of the
56800E core.
8
Up to 54 general-purpose I/O (GPIO) pins
— 5 V tolerant I/O
— Individual control for each pin to be in peripheral or GPIO mode
— Individual input/output direction control for each pin in GPIO mode
— Individual control for each output pin to be in push-pull mode or open-drain mode
— Hysteresis and configurable pullup device on all input pins
— Ability to generate interrupt with programmable rising or falling edge and software interrupt
— Configurable drive strength: 4 mA / 8 mA sink/source current
JTAG/EOnCE debug programming interface for real-time debugging
— IEEE 1149.1 Joint Test Action Group (JTAG) interface
— EOnCE interface for real-time debugging
Low-speed run, wait, and stop modes: as low as 781 Hz clock provided by OCCS and internal ROSC
Large regulator standby mode available for reducing power consumption at low-speed mode
Less than 30 µs typical wakeup time from stop modes
Each peripheral can be individually disabled to save power
Award-Winning Development Environment
Architecture Block Diagram
Power Saving Features
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Figure 1
and
Figure
2.
Figure 1
illustrates how the 56800E system
Freescale Semiconductor

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