MCIMX515DVK8C Freescale Semiconductor, MCIMX515DVK8C Datasheet - Page 86

• Manufacturer Part Number: MCIMX515DVK8C
• Description: IC MPU I.MX51 527MABGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515DVK8C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 257-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Eeprom Size: -
• Data Converters: -

Electrical Characteristics
86
DISPx_DAT10
DISPx_DAT12
DISPx_DAT13
DISPx_DAT14
DISPx_DAT15
DISPx_DAT16
DISPx_DAT17
DISPx_DAT18
DISPx_DAT19
DISPx_DAT20
DISPx_DAT21
DISPx_DAT11
DISPx_DAT0
DISPx_DAT1
DISPx_DAT2
DISPx_DAT3
DISPx_DAT4
DISPx_DAT5
DISPx_DAT6
DISPx_DAT7
DISPx_DAT8
DISPx_DAT9
Port Name
i.MX51
(x=1,2)
(General)
DAT[10]
DAT[12]
DAT[13]
DAT[14]
DAT[15]
DAT[16]
DAT[17]
DAT[18]
DAT[19]
DAT[20]
DAT[21]
DAT[11]
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
DAT[8]
DAT[9]
Signal
Name
RGB,
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
16-bit
RGB
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
R[0]
R[1]
R[2]
R[3]
R[4]
B[0]
B[1]
B[2]
B[3]
B[4]
—
—
—
—
—
—
RGB/TV Signal Allocation (Example)
18-bit
RGB
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
—
—
—
—
Table 79. Video Signal Cross-Reference
24-bit
RGB
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
LCD
YCrCb
Y/C[0]
Y/C[1]
Y/C[2]
Y/C[3]
Y/C[4]
Y/C[5]
Y/C[6]
Y/C[7]
8-bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
YCrCb
16-bit
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
—
—
—
—
—
—
YCrCb
20-bit
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
C[8]
C[9]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
Y[9]
—
—
DAT[10]
DAT[12]
DAT[13]
DAT[14]
DAT[15]
DAT[11]
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
Signal
DAT[8]
DAT[9]
Smart
Name
—
—
—
—
—
—
The restrictions are as follows:
a) There are maximal three
continuous groups of bits that
could be independently mapped to
the external bus.
Groups should not be overlapped.
b) The bit order is expressed in
each of the bit groups, for example
B[0] = least significant blue pixel
bit
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