MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 253

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6.12.5.4
Freescale Semiconductor
Reset
32–51
52–53
54–57
58–63
SPR 627
Bits
Bits
59
60
61
62
63
W
R
32
PERMIS Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write, and execute permission bits.
U0–U3
Name
Name
RPN
—
W
M
G
E
I
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MAS Register 3 (MAS3)
Table 6-30. MAS2 Field Descriptions—EPN and Page Attributes (continued)
Write-through
0 This page is considered write-back with respect to the caches in the system.
1 All stores performed to this page are written through the caches to main memory.
Caching-inhibited
0 Accesses to this page are considered cacheable.
1 The page is considered caching-inhibited. All loads and stores to the page bypass the caches and are
Memory coherency required
0 Memory coherency is not required.
1 Memory coherency is required. This allows loads and stores to this page to be coherent with loads and
Guarded
0 Accesses to this page are not guarded and can be performed before it is known if they are required by
1 All loads and stores to this page that miss in the L1 cache are performed without speculation (that is, they
Endianness. Determines endianness for the corresponding page. Little-endian operation is true little endian,
which differs from the modified little-endian byte-ordering model optionally available in previous devices that
implement the original PowerPC architecture. See the PowerPC™ e500 Core Family Reference Manual for
more information.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
that represent offsets within a page are ignored and should be cleared. For the e500v2, the 4 high-order bits
of RPN are stored in MAS7[RPN].
hold information useful to a page-scanning algorithm or mark more abstract page attributes.
Real page number. Depending on page size, only the bits associated with a page boundary are valid. Bits
Reserved, should be cleared.
User attribute bits. Associated with a TLB entry and can be used by system software. For example, they can
performed directly to main memory.
stores from other processors (and devices) in the system, assuming all such devices are participating in
the coherency protocol.
the sequential execution model.
are known to be required). Speculative loads can be performed if they hit in the L1 cache. In addition,
accesses to caching-inhibited pages are performed using only the memory element that is explicitly
specified.
Table 6-31. MAS3 Field Descriptions–RPN and Access Control
RPN
Figure 6-46. MAS Register 3 (MAS3)
All zeros
Description
Description
51 52 53 54
—
U0–U3
Access: Supervisor read/write
57
UX SX UW SW UR SR
58
Core Register Summary
59
60
61
62
6-37
63