MPC8533EVTARJA Freescale Semiconductor, MPC8533EVTARJA Datasheet - Page 8

• Manufacturer Part Number: MPC8533EVTARJA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Features
2.3
Key features of the MPC8533E include:
2.4
The following sections cover the numerous features of the device in greater detail.
2.4.1
The MPC8533E contains a high-performance 32-bit Book E–enhanced e500v2 core that implements the
PowerPC architecture. In addition to 36-bit physical addressing, this version of the e500 core includes:
The MPC8533E also contains 256 Kbytes of L2 cache/SRAM, as follows:
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High-performance PowerPC e500v2 core with 36-bit physical addressing
Separate 32-Kbyte level-1 instruction and data caches; 256 Kbytes of level-2 cache
Integrated security engine with XOR acceleration
Two integrated 10/100/1Gb enhanced three-speed Ethernet controllers (eTSECs) with TCP/IP
acceleration and classification capabilities
DDR/DDR2 SDRAM memory controller
32-bit PCI controller
Three PCI Express controllers: Dual x4/x2/x1 interfaces and single x1 interface
Programmable interrupt controller (PIC)
Four-channel DMA controller
Two I
DUART
Local bus controller (LBC)
16 general-purpose I/O signals (8 dedicated input; 8 dedicated output)
Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit general-purpose registers.
Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for
single-precision (32-bit) floating-point instructions.
Eight-way set-associative cache organization with 32-byte cache lines
Flexible configuration (can be configured as part cache, part SRAM)
External masters can force data to be allocated into the cache through programmed memory ranges
or special transaction types (stashing).
SRAM features include the following:
— I/O devices access SRAM regions by marking transactions as snoopable (global).
— Regions can reside at any aligned location in the memory map.
— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line
Chip-Level Features
Module Features
accesses.
e500 Core and Memory Unit
2
C controllers
MPC8533E Integrated Host Processor Product Brief, Rev. 0
Freescale Semiconductor