IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 22

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

3.2.4
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 32H...) can be set to choose 75 Ω, 100 Ω,
110 Ω or 120 Ω internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
components to connect with the cable for one channel.
Table-14 Impedance Matching for Transmitter
3.2.5
T_OFF bit (TCF0, 22H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
3.2.6
or not. This selection is made by the TJA_E bit (TJACF, 21H...).
Figure
FUNCTIONAL DESCRIPTION
IDT82P5088
Jittered Clock
The transmit line interface consists of TTIPn pin and TRINGn pin. The
Note: The precision of the resistors should be better than ± 1%
The transmit path can be powered down individually by setting the
The Transmit Jitter Attenuator of each link can be chosen to be used
The Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Jittered Data
Cable Configuration
7.
TRANSMIT PATH LINE INTERFACE
TRANSMIT PATH POWER DOWN
TRANSMIT JITTER ATTENUATOR
T1/133~266 ft
T1/266~399 ft
T1/399~533 ft
T1/533~655 ft
-15.0 dB LBO
-22.5 dB LBO
-7.5 dB LBO
T1/0~133 ft
J1/0~655 ft
E1/120 Ω
0 dB LBO
E1/75 Ω
pointer
Figure-7 Jitter Attenuator
write
32/64/128
DPLL
FIFO
Figure-9
T_TERM[2:0]
shows the appropriate external
000
001
010
011
010
pointer
read
Internal Termination
De-jittered Data
Table-14
De-jittered Clock
PULS[3:0]
0000
0001
0010
0100
0101
1000
1001
1010
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
0011
0110
0111
1011
is the list
22
of the recommended impedance matching for transmitter.
ing THZ pin to high or individually by setting the T_HZ bit (TCF1, 23H...) to
‘1’. In this state, the internal transmit circuits are still active.
impedance:
•
•
•
•
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the TJA_DP[1:0]
bits (TJACF, 21H...). Accordingly, the constant delay produced by the
Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-bit FIFO is used
when large jitter tolerance is expected, and the 32-bit FIFO is used in
delay sensitive applications.
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF). The jitter which
frequency is lower than the CF passes through the DPLL without any
attenuation. In T1/J1 applications, the CF of the DPLL can be 5 Hz or
1.26 Hz, as selected by the TJA_BW bit (TJACF, 21H...). In E1 applica-
tions, the CF of the DPLL can be 6.77 Hz or 0.87 Hz, as selected by the
TJA_BW bit (TJACF, 21H...). The lower the CF is, the longer time is
needed to achieve synchronization.
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow or underflow is captured by the
0 Ω
R
The TTIPn/TRINGn can be turned into high impedance globally by pull-
Besides, in the following cases, TTIPn/TRINGn will also become high
The FIFO is used as a pool to buffer the jittered input data, then the
The DPLL is used to generate a de-jittered clock to clock out the data
If the incoming data moves faster than the outgoing data, the FIFO
T
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;·
Loss of TCLKn: corresponding TTIPn/TRINGn become HZ (excep-
tions: Remote Loopback; Transmit internal pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
T_TERM[2:0]
1XX
-
External Termination
PULS[3:0]
0001
0001
-
February 5, 2009
9.4 Ω
R
-
T