SC16C850LIBS,128 NXP Semiconductors, SC16C850LIBS,128 Datasheet - Page 40

• Manufacturer Part Number: SC16C850LIBS,128
• Description: IC UART SINGLE W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C850LIBS,128

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 2.5V
• With Parallel Port: *
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 38.
T
[1]
[2]
[3]
SC16C850L
Product data sheet
Symbol
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
N
WH
WL
w(clk)
XTAL1
su(A)
h(A)
su(RWL-CSL)
su(RWH-CSL)
w(CS)
d(CS)
d(CS-Q)
dis(CS-QZ)
h(CS-RWH)
d(RW)
su(D-CSH)
h(CSH-D)
d(modem-IRQL)
d(CS-IRQH)R
d(stop-IRQL)
d(CS-TX)W
d(start-IRQL)
d(CS-IRQH)W
d(CS-Q)W
w(RESET_N)
amb
Applies to external clock, crystal oscillator max 24 MHz.
Maximum frequency =
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
=

40

Dynamic characteristics - Motorola or 68 mode
C to +85
Parameter
pulse width HIGH
pulse width LOW
clock pulse width
frequency on pin XTAL1
address set-up time
address hold time
set-up time from R/W LOW to CS LOW
set-up time from R/W HIGH to CS LOW
CS pulse width
CS delay time
delay time from CS to data output
disable time from CS to high-impedance
data output
hold time from CS to R/W HIGH
R/W delay time
set-up time from data input to CS HIGH
data input hold time after CS HIGH
delay time from modem to IRQ LOW
read delay time from CS to IRQ HIGH
delay time from stop to IRQ LOW
write delay time from CS to TX
delay time from start to IRQ LOW
write delay time from CS to IRQ HIGH
write delay time from CS to data output
pulse width on pin RESET
baud rate divisor

C; V
-------------- -
t
w clk
DD

1
= 1.65 V to 1.95 V; unless otherwise specified.

All information provided in this document is subject to legal disclaimers.
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 5 — 1 February 2011
25 pF load
25 pF load
Conditions
25 pF load
25 pF load
[1][2]
[3]
[3]
[3]
Min
6
6
12.5
-
5
10
10
10
20
10
-
-
5
10
5
5
-
-
-
8T
-
-
-
10
1
RCLK
SC16C850L
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2011. All rights reserved.
Max
-
-
-
80
-
-
-
-
-
-
40
20
-
-
-
-
50
50
1T
24T
1T
50
50
-
(2
16
RCLK
RCLK
RCLK
 1)
40 of 55
Unit
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
ns
ns
ns