74AUP2G132GD,125 NXP Semiconductors, 74AUP2G132GD,125 Datasheet - Page 2

• Manufacturer Part Number: 74AUP2G132GD,125
• Description: IC SCHMITT TRIG NAND 2IN XSON8U
• Manufacturer: NXP Semiconductors

Specifications of 74AUP2G132GD,125

• Product: NAND
• Number Of Gates: 2
• Propagation Delay Time: 6.2 ns, 6.8 ns, 8.7 ns, 10.7 ns, 16.6 ns
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: XSON-8U
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5405-2

NXP Semiconductors
4. Ordering information
Table 1.
5. Marking
Table 2.
[1]
6. Functional diagram
74AUP2G132
Product data sheet
Type number
74AUP2G132DC
74AUP2G132GT
74AUP2G132GF
74AUP2G132GD
74AUP2G132GM
74AUP2G132GN
74AUP2G132GS
Type number
74AUP2G132DC
74AUP2G132GT
74AUP2G132GF
74AUP2G132GD
74AUP2G132GM
74AUP2G132GN
74AUP2G132GS
Fig 1.
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Logic symbol
1A
1B
2A
2B
Ordering information
Marking codes
Package
Temperature range Name
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
001aah880
1Y
2Y
All information provided in this document is subject to legal disclaimers.
Fig 2.
VSSOP8
XSON8
XSON8
XSON8U
XQFN8U
XSON8
XSON8
Rev. 4 — 4 November 2010
IEC logic symbol
Description
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1 × 0.5 mm
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 × 1.0 × 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 × 1.0 × 0.35 mm
&
&
001aah881
Marking code
aE2
aE2
aE
aE2
aE2
aE
aE
Low-power dual 2-input NAND Schmitt trigger
[1]
Fig 3.
A
B
74AUP2G132
Logic diagram (one gate)
© NXP B.V. 2010. All rights reserved.
001aac532
Version
SOT765-1
SOT833-1
SOT1089
SOT996-2
SOT902-1
SOT1116
SOT1203
Y
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