74AUP2G06GF,132 NXP Semiconductors, 74AUP2G06GF,132 Datasheet - Page 18
![IC GATE NOR DUAL 2INPUT XSON8](/photos/39/72/397279/inhouse_4aup2g06gf132_t_sml.jpg)
74AUP2G06GF,132
Manufacturer Part Number
74AUP2G06GF,132
Description
IC GATE NOR DUAL 2INPUT XSON8
Manufacturer
NXP Semiconductors
Datasheet
1.74AUP2G06GF132.pdf
(18 pages)
Specifications of 74AUP2G06GF,132
Number Of Circuits
2
Logic Family
74AUP
Propagation Delay Time
4 ns, 4.3 ns, 6.3 ns, 7.8 ns, 12 ns
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Package / Case
XSON-6
Mounting Style
SMD/SMT
Operating Supply Voltage
0.8 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5398-2
NXP Semiconductors
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Low-power dual inverter with open-drain output
74AUP2G06
Document identifier: 74AUP2G06
Date of release: 26 October 2010
All rights reserved.