74LVC2G06GF,132 NXP Semiconductors, 74LVC2G06GF,132 Datasheet

IC INVERTER DUAL BUFFER XSON6

74LVC2G06GF,132

Manufacturer Part Number
74LVC2G06GF,132
Description
IC INVERTER DUAL BUFFER XSON6
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC2G06GF,132

Number Of Circuits
2
Logic Family
74LVC
Logic Type
CMOS
Propagation Delay Time
3.7 ns, 4.3 ns, 4.9 ns, 5.3 ns, 8.2 ns
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Package / Case
XSON-6
Mounting Style
SMD/SMT
Operating Supply Voltage
1.65 V to 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-5466-2
1. General description
2. Features and benefits
The 74LVC2G06 provides two inverting buffers.
The output of this device is an open drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
74LVC2G06
Inverters with open-drain outputs
Rev. 4 — 28 October 2010
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
−24 mA output drive (V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74LVC2G06GF,132 Summary of contents

Page 1

Inverters with open-drain outputs Rev. 4 — 28 October 2010 1. General description The 74LVC2G06 provides two inverting buffers. The output of this device is an open drain and can be connected to other open-drain outputs to implement active-LOW ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC2G06GW −40 °C to +125 °C 74LVC2G06GV −40 °C to +125 °C 74LVC2G06GM −40 °C to +125 °C 74LVC2G06GF −40 °C to +125 °C 74LVC2G06GN −40 °C to +125 °C 74LVC2G06GS 4 ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC2G06 GND 001aab668 Fig 4. Pin configuration SOT363 and SOT457 6.2 Pin description Table 3. Pin description Symbol Pin 1A 1 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level high-impedance OFF-state. 8. Limiting values Table 5 ...

Page 4

... NXP Semiconductors Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter I output clamping current OK V output voltage O I output current O I supply current CC I ground current GND T storage temperature ...

Page 5

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input IH voltage V LOW-level input IL voltage V LOW-level output OL voltage I input leakage current OFF-state output OZ current I power-off leakage OFF ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +125 °C T amb V HIGH-level input IH voltage V LOW-level input IL voltage V LOW-level output OL voltage I input leakage current OFF-state output OZ current I power-off leakage OFF current I supply current CC Δ ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see power dissipation capacitance [1] Typical values are measured the same as t and PLZ PZL [ used to determine the dynamic power dissipation (P PD × ...

Page 8

... NXP Semiconductors Table 9. Measurement points Supply voltage Input 0.5 × 1.95 V 0.5 × 2.7 V 2.7 V 1 3.6 V 1.5 V 0.5 × 5.5 V Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance. ...

Page 9

... NXP Semiconductors 13. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 0.30 1.1 0.25 mm 0.1 0.20 0.8 0.10 OUTLINE VERSION IEC SOT363 Fig 9. Package outline SOT363 (SC-88) 74LVC2G06 Product data sheet scale 2.2 1.35 2 ...

Page 10

... NXP Semiconductors Plastic surface-mounted package (TSOP6); 6 leads y 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) UNIT 0.1 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT457 Fig 10. Package outline SOT457 (TSOP6) 74LVC2G06 Product data sheet scale 3.1 1.7 3 ...

Page 11

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 12

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 12 ...

Page 13

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 14

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 15

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC2G06 v.4 20101028 • Modifications: Added type number 74LVC2G06GN (SOT1115/XSON6 package). • ...

Page 16

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 17

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC2G06 Product data sheet 16 ...

Page 18

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline ...

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