PC28F640P33B85A NUMONYX, PC28F640P33B85A Datasheet - Page 59

• Manufacturer Part Number: PC28F640P33B85A
• Description: IC FLASH 64MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F640P33B85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 22b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888226; 888226; PC28F640P33B85; PC28F640P33B85 888226

Numonyx™ StrataFlash
11.3.3
November 2007
Order Number: 314749-05
available; if cleared, the buffer is not available. To retry, issue the Buffered
Programming Setup command again, and re-check SR[7]. When SR[7] is set, the
buffer is ready for loading. (see
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing
a 32-word boundary during programming will double the total programming time.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and SR[7,5,4] are set. If an error occurs while writing to the array, the device
stops programming, and SR[7,4] are set, indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with V
(see
device with V
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and SR[5,4] are set.
If Buffered programming is attempted while V
errors are detected that have set Status Register bits, the Status Register should be
cleared using the Clear Status Register command.
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see
Flowchart” on page
across 32 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 32 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR[0] indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 32-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
Section 5.2, “Operating Conditions” on page 26
®
Embedded Memory (P33)
PP
= V
PPH
72). It uses a write buffer to spread MLC program performance
).
Figure 35, “Buffer Program Flowchart” on page
PP
is below V
for limitations when operating the
PPLK
, SR[4,3] are set. If any
PP
Figure 36, “BEFP
= V
PPL
or V
Datasheet
71).
PPH
59