X28HC64J-12 Intersil, X28HC64J-12 Datasheet - Page 8
![IC EEPROM 64KBIT 120NS 32PLCC](/photos/18/29/182917/x28hc64j-12_sml.jpg)
X28HC64J-12
Manufacturer Part Number
X28HC64J-12
Description
IC EEPROM 64KBIT 120NS 32PLCC
Manufacturer
Intersil
Datasheet
1.X28HC64D-12.pdf
(17 pages)
Specifications of X28HC64J-12
Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
120ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
32-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
X28HC64J-12
Manufacturer:
XICOR
Quantity:
3 198
Company:
Part Number:
X28HC64J-12
Manufacturer:
XICOR
Quantity:
5 510
Part Number:
X28HC64J-12
Manufacturer:
XICOR
Quantity:
20 000
Company:
Part Number:
X28HC64J-12T1
Manufacturer:
INTERSIL
Quantity:
4 219
Part Number:
X28HC64J-12TZ
Manufacturer:
INTERSIL
Quantity:
20 000
System Considerations
Because the X28HC64 is frequently used in large memory
arrays, it is provided with a two-line control architecture for
both read and write operations. Proper usage can provide
the lowest possible power dissipation, and eliminate the
possibility of contention where multiple I/O pins share the
same bus.
To gain the most benefit, it is recommended that CE be
decoded from the address bus, and be used as the primary
device selection input. Both OE and WE would then be
common among all devices in the array. For a read
operation, this assures that all deselected devices are in
their standby mode, and that only the selected device(s)
is/are outputting data on the bus.
FIGURE 10. NORMALIZED I
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0M
5.5V
OVER FREQUENCY DATA PROTECTION
CC
FREQUENCY (Hz)
CC
8
(RD) BY TEMPERATURE
10M
- 55°C
+ 125°C
+ 25°C
20M
X28HC64
Because the X28HC64 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes.
The magnitude of these spikes is dependent on the output
capacitive loading of the I/Os. Therefore, the larger the array
sharing a common bus, the larger the transient spikes. The
voltage peaks associated with the current transients can be
suppressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended
that a 0.1µF high frequency ceramic capacitor be used
between V
size of the array, the value of the capacitor may have to be
larger.
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between V
devices employed in the array. This bulk capacitor is
employed to overcome the voltage droop caused by the
inductive effects of the PC board traces.
FIGURE 11. NORMALIZED I
1.4
1.2
1.0
0.8
0.6
0.4
0.2
CC
0M
RANGE AND FREQUENCY
and V
SS
at each device. Depending on the
FREQUENCY (Hz)
CC
(RD) @ 25% OVER THE V
CC
10M
and V
4.5V
5.0V
CC
5.5V
CC
SS
CC
for each eight
August 28, 2009
FN8109.2
CC
20M