CY7C1520KV18-200BZC Cypress Semiconductor Corp, CY7C1520KV18-200BZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1520KV18-200BZC
• Description: IC SRAM 72MBIT 200MHZ 165-FPBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1520KV18-200BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Contents
Pin Configuration ............................................................. 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Burst Address Table
(CY7C1518KV18, CY7C1520KV18) ................................ 11
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Electrical Characteristics ...................................... 16
Document Number: 001-00437 Rev. *J
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Single Clock Mode ...................................................... 9
DDR Operation............................................................ 9
Depth Expansion ......................................................... 9
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
PLL ............................................................................ 10
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Test Data-Out (TDO)................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes........................................................... 18
Boundary Scan Order .................................................... 19
Power Up Sequence in DDR II SRAM ........................... 20
Maximum Ratings........................................................... 21
Operating Range ............................................................ 21
Neutron Soft Error Immunity......................................... 21
Electrical Characteristics .............................................. 21
Capacitance .................................................................... 24
Thermal Resistance ....................................................... 24
Switching Characteristics ............................................. 25
Switching Waveforms .................................................... 27
Ordering Information .................................................... 28
Package Diagram ........................................................... 30
Acronyms........................................................................ 31
Document Conventions ................................................. 31
Document History Page................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Power Up Sequence ................................................. 20
PLL Constraints......................................................... 20
DC Electrical Characteristics..................................... 21
AC Electrical Characteristics..................................... 23
Ordering Code Definition........................................... 29
Units of Measure ....................................................... 31
Worldwide Sales and Design Support....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Page 4 of 33
[+] Feedback