FAN73933M Fairchild Semiconductor, FAN73933M Datasheet - Page 15

• Manufacturer Part Number: FAN73933M
• Description: IC GATE DVR HALF BRIDGE 14-SOIC
• Manufacturer: Fairchild Semiconductor
• Type: Half-Bridge Gate Drive ICr

Specifications of FAN73933M

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 160ns
• Current - Peak: 2.5A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 600V
• Voltage - Supply: 10 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (0.154", 3.90mm Width)
• Product: Half-Bridge Drivers
• Rise Time: 40 ns
• Fall Time: 20 ns
• Propagation Delay Time: 160 ns
• Supply Voltage (max): 20 V
• Supply Voltage (min): 10 V
• Supply Current: 0.9 mA
• Maximum Power Dissipation: 1 W
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Driver Configuration: Non-Inverting
• Driver Type: High and Low Side
• Operating Supply Voltage (max): 20V
• Peak Output Current: 2.5A
• Power Dissipation: 1W
• Operating Supply Voltage (min): 10V
• Turn Off Delay Time: 50ns
• Turn On Delay Time (max): 50ns
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 14
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FAN73933 • Rev. 1.0.0
© 2009 Fairchild Semiconductor Corporation
The FAN73933 has a negative V
curve, as shown in Figure 43.
Even though the FAN73933 has been shown able to
handle these negative V
strongly recommended that the circuit designer limit the
negative V
PCB layout to minimize the value of parasitic elements
and component use. The amplitude of negative V
age is proportional to the parasitic inductances and the
turn-off speed, di/dt, of the switching device.
General Guidelines
Printed Circuit Board Layout
The layout recommended for minimized parasitic ele-
ments is as follows:
Direct tracks between switches with no loops or devia-
tion.
Avoid interconnect links. These can add significant
inductance.
Reduce the effect of lead-inductance by lowering
package height above the PCB.
Consider co-locating both power switches to reduce
track length.
To minimize noise coupling, the ground plane should
not be placed under or near the high-voltage floating
side.
To reduce the EM coupling and improve the power
switch turn-on/off performance, the gate drive loops
must be reduced as much as possible.
Figure 43. Negative V
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0
S
100
transient as much as possible by careful
200
300
Pulse Width [ns]
400
S
S
Transient Chracteristic
500
tranient conditions, it is
S
600
transient performance
700
800
900 1000
S
volt-
15
Placement of Components
The recommended selection of component is as follows:
It is stongly recommended that the placement of compo-
nents is as follows:
Place a bypass capacitor between the V
pins. A ceramic 1µF capacitor is suitable for most
applications. This component should be placed as
close as possible to the pins to reduce parasitic ele-
ments.
The bypass capacitor from V
the low-side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
The bootstrap resistor, R
sizing the bootstrap resistance and the current devel-
oped during initial bootstrap charge. If the resistor is
needed in series with the bootstrap diode, verify that
V
use is typically 5 ~ 10Ω, which increases the V
constant. If the votage drop of the bootstrap resistor
and diode is too high or the circuit topology does not
allow a sufficient charging time, a fast recovery or
ultra-fast recovery diode can be used.
The bootstrap capacitor, C
capacitor, such as a ceramic capacitor.
Place components tied to the floating voltage pins (V
and V
the device and the FAN73933. NC (not connected)
pins in this package maximize the distance between
the high-voltage and low-voltage pins (see Figure 3.).
Place and route for bypass capacitors and gate resis-
tors as close as possible to gate drive IC.
Locate the bootstrap diode, D
ble to bootstrap capacitor, C
The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra-fast diode.
B
does not fall below COM (ground). Recommended
S
) near the respective high-voltage portions of
BOOT
BOOT
BOOT
CC
, must be considered in
BOOT
, uses a low-ESR
to COM supports both
.
, as close as possi-
www.fairchildsemi.com
DD
and V
BS
time
SS
B