PM6652 STMicroelectronics, PM6652 Datasheet
PM6652
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... CPU and the graphics core (render engine) of the Intel® mobile platform, according with Intel MVP6.5 specifications. The PM6652 can also be configured to supply the 7-bit family, VR11 compliant, ATOM® processors. The controller, based on constant on-time (COT) architecture, allows real-time dynamic switching ...
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... Differential remote sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.6 Voltage dynamic (VID) transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7 Current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.8 Soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.9 Internal MOS drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.10.1 2/53 Constant on time PWM architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output ripple compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Doc ID 16867 Rev 3 PM6652 ...
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... PM6652 8.10.2 8.10.3 8.10.4 8.10.5 8.10.6 8.10.7 8.10.8 8.11 System accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.11.1 8.11.2 9 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 Load transient response improvement with feedback capacitor . . . . . . . . 44 9.2 Voltage regulation without droop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Current monitor (IMON Thermal throttling ...
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... VCORE efficiency (DPRSLPVR high and low Figure 23. VCORE load regulation - droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 24. Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 25. PM6652 integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 26. PM6652 droop function Figure 27. GFX supply - VID step, skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 28. CPU IMVP6.5 - VID step, skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 29. Precision resistor current sensing Figure 30. ...
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... PM6652 Figure 49. No load-line output reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 50. Load line disabled – VCCIO Supply example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 51. VCCIO output voltage ripple ( Figure 52. VCCIO output voltage ripple ( Figure 53. Load transient response - 5 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 54. Load transient response - 40 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 55. Load transient response - 100 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 56 ...
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... Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. VID for INTEL MVP 6.5 GFX core and CPU operation mode Table 7. Voltage identification (VID) for INTEL VR11 operation mode . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. PM6652 mode of operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9. VFQFPN 5x5x1.0 mm 32L pitch 0.50 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6/53 ...
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... PM6652 1 Typical application circuit Figure 1. Typical application circuit - IMVP6.5 render core supply Figure 2. Typical application circuit - IMVP6.5 LV/ULV CPU supply Doc ID 16867 Rev 3 Typical application circuit 7/53 ...
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... Typical application circuit Figure 3. Typical application circuit – VR11 Atom CPU supply 8/53 Doc ID 16867 Rev 3 PM6652 ...
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... PM6652 2 Pin settings 2.1 Connections Figure 4. PM6652 pin out (top view) 2.2 Pin description Figure 5. Pin functions Pin n° Name 1 VRTT# 2 THERM 3 GSNS 4 VSNS 5 CSNS 6 VOUT 7 COMP 8 SVCC 9 SGND Description Thermal throttling indicator, open-drain output. Thermal throttling input. Connect to the central tap of NTC-based divider for MOS or inductor thermal monitoring ...
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... VID0 is the LSB and VID6 the MSB. Connect VIDx to a voltage <0.33V to program a ‘0’; connect VIDx to a voltage >0.77V to program a ‘1’. Exposed pad. Connect to SGND. Doc ID 16867 Rev 3 PM6652 ...
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... PM6652 3 Electrical data 3.1 Maximum rating Table 2. Absolute maximum ratings Symbol V PVCC to PGND PVCC V SVCC to SGND SVCC SGND to PGND V BOOT to PHASE BOOT V HGATE to PHASE HGATE V PHASE to PGND PHASE V LGATE to PGND LGATE VRTT#, THERM, GSNS, VSNS, CSNS, VOUT, COMP, VDAC, IMON, IMONFB, ILIM, OSC, PWRGD, ...
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... Electrical data 3.3 Recommended operating conditions Table 4. Recommended operating conditions Symbol V Input voltage range IN V PVCC Voltage range PVCC 12/53 Parameter Doc ID 16867 Rev 3 PM6652 Value Unit Min Typ Max 4 4.5 - 5.5 V ...
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... PM6652 4 Electrical characteristics ° +12 V, PVCC = + not otherwise specified Table 5. Electrical characteristics Symbol Parameter Supply section I IC supply current SVCC,QUIESCENT Operating current in I SVCC,SHDN shutdown SVCC undevoltage lockout upper threshold V UVLO SVCC undervoltage SVCC lockout lower threshold UVLO hysteresis ON-time T On-time duration ...
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... CSNS OUT RIMONFB=1.8kΩ, RIMON=10kΩ V – 15mV; CSNS OUT RIMONFB=1.8kΩ, RIMON=10kΩ 8 kΩ <RIMON<16 kΩ; GSNS-AGND<20mV I = 0µA IMON SSTART pin connected to AVCC Doc ID 16867 Rev 3 PM6652 Min. Typ. Max. Unit 1 µ 4.5 5 5.5 µA -3.5 3.5 mV Ω ...
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... PM6652 Table 5. Electrical characteristics (continued) Symbol Parameter Soft-end section VCC_GFX discharge resistance Thermal throttling management Thermal detection trip THERM threshold Threshold hysteresis VRTT# Output on resistance I VRTT# leakage current VRTT# forced to 3.3V; THERM=5V VRTT# Power management SW regulator enable turn on level COREON SW regulator enable ...
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... Doc ID 16867 Rev 3 PM6652 VCORE 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 ...
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... PM6652 Table 6. VID for INTEL MVP 6.5 GFX core and CPU operation mode (continued) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCORE VID6 VID5 VID4 VID3 VID2 VID1 VID0 0 0 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 ...
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... Doc ID 16867 Rev 3 PM6652 VCORE 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 ...
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... PM6652 Table 7. Voltage identification (VID) for INTEL VR11 operation mode (continued) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCORE VID6 VID5 VID4 VID3 VID2 VID1 VID0 1 0 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 ...
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... Figure 6. V turn on and PGOOD rising - CORE No load Figure 8. V working mode - DPRSLPVR CORE asserted, no load 20/ 320 kHz CORE Figure 7. Figure 9. Doc ID 16867 Rev 3 = 1.2375 V, DPRSLPVR = not V turn on- CPU IMVP6.5 mode CORE V working mode (0 CORE DPRSLPVR asserted, no load PM6652 ...
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... PM6652 Figure 10. V working mode (0 CORE DPRSLPVR asserted, no load Figure 12. V working mode - DPRSLPVR CORE not asserted load Figure 14. V working mode (0 CORE DPRSLPVR not asserted, no load Typical operating characteristics Figure 11. V CORE not asserted, no load Figure 13. V CORE DPRSLPVR not asserted, no load Figure 15 ...
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... Figure 18. V VID step variation - VR11 CORE mode Figure 20. V overvoltage (+200 mV) CORE 22/53 Figure 17. Droop function - transient response Figure 19. V CORE deassertion and PGOOD transition Figure 21. V CORE Doc ID 16867 Rev 3 PM6652 soft end - COREON pin undervoltage (-300 mV) ...
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... PM6652 Figure 22. V efficiency (DPRSLPVR high CORE and low) Typical operating characteristics Figure 23. V CORE function Doc ID 16867 Rev 3 load regulation - droop 23/53 ...
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... Block diagram 7 Block diagram Figure 24. Simplified block diagram 24/53 Doc ID 16867 Rev 3 PM6652 ...
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... In order to maximize the efficiency at very light load, a pulse skipping control algorithm is performed. The PM6652 is also fully compliant with the fast and slow render suspend state exit mode, as required by IMVP 6.5 spec. for render core supply (see dynamic (VID) transitions on page 30 ...
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... OUT OUT ≅ τ OUT ON K OSC V OSC V R α OSC INT OSC + INT Doc ID 16867 Rev 3 PM6652 τ Section 8.5: section for details about the 1 α ⋅ OSC K OSC OSC ...
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... A minimum on-time (70 ns) is also introduced to assure the start-up switching sequence. PM6652 has a one-shot generator that turns on the high side MOSFET when the following conditions are satisfied simultaneously: The PWM comparator is high; ...
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... Device description Figure 25. PM6652 integrator 8.2 Mode selection The PM6652 has two multifunction pins which allow selecting the supply mode of operation. There are three different modes, as shown in table Table 8. PM6652 mode of operation selection Feature VDAC Table VOUT minimum voltage slew-rate VBOOT voltage ...
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... PM6652 8.3 Pulse-skip working mode The PM6652 can obtain very high efficiency at light load if the low side MOSFET is turned off when the inductor current becomes equal to zero. This feature is performed by the zero crossing comparator (see the internal block diagram, VR11 mode this feature is activated by asserting DPRSLPVR pin. In GFX render mode the DPRSLPVR assertion implies also that the VDAC minimum slew-rate is 10mV/µ ...
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... Device description Figure 26. PM6652 droop function 8.6 Voltage dynamic (VID) transitions The integrated 7 bit digital-to-analog converter (DAC) can change its output voltage, with 12.5 mV step, following converter starts an internal bit rolling in order to ramp-up (or ramp-down) the VDAC output with a minimum voltage slew-rate as declared in for a blanking time (typ.30 µ ...
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... PM6652 very high efficiency at light load. inductor current waveform when the DPRSLPVR pin is asserted high or low. When the DPRSLPVR control pin is still asserted high and the VDAC ramp-up transition is requested, the render suspend fast exit is performed, by increasing VDAC output with a minimum voltage slew-rate of 10 mV//µ the DPRSLPVR signal is de-asserted before any VIDs change, the VDAC ramp-up transition is performed with a minimum voltage slew-rate of 5 mV/µ ...
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... CA capacitor can be computed as follows: Equation 12 In PM6652 the CSNS and VOUT inputs are high-impedance pins so a very small leakage current can be measured, in the range 100 nA. This leakage current, sourced by CSNS, is multiplied by the equivalent resistance measured across CA capacitor, i.e. ...
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... PM6652 RA//RB1, and the resultant voltage drop is found on the VCORE output voltage, in agreement with Equation 7 Equation 13 The result is an output voltage drop also at no load. In order to avoid this no-load voltage drop condition, the current sensing filter equivalent resistance, i.e. RA//RB1, should fall in the range 1 kΩ÷10 kΩ. ...
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... MOSFET is turned-on. See and page 22 Figure 19 on page 22 Figure 36. VDAC soft-start voltage slew-rate vs capacitor value 34/53 Figure 35. IMPV6.5 CPU mode start-up show the different turn-on behavior for GFX mode and for the soft-end waveforms details. Doc ID 16867 Rev 3 PM6652 Figure 18 on ...
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... The BOOT and PHASE pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly fed through PVCC and PGND pins. An important feature of the PM6652 gate drivers is the adaptive anti-cross-conduction circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same time ...
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... Equation 16 Figure 37. Average current limit - recovery In order to set the right average current limit threshold, the PM6652 internal parameters and also external components accuracy must be considered. A complete equation for the average current limit threshold worst case variation is: Equation 17 δ ...
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... FILT IMON The IMON voltage is limited to 1.15 V (maximum value), as required by IMVP6.5 specifications, in order to avoid any damage to the CPU. This feature is performed by limiting the current injected by the PM6652 IMON pin into RIMON resistor. Figure 39. Current monitor with external components 8.10.3 Thermal throttling The voltage regulator thermal throttling function is used by the CPU in order to avoid catastrophic thermal damage ...
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... In application where this function is not required (in render core supply, for example) the THERM pin must be connected and VRTT# can be left floating. Figure 40. Voltage regulator thermal throttling 8.10.4 Overvoltage protection The PM6652 can detect two kinds of VOUT overvoltage: ● Fixed 1.55 V overvoltage threshold; ● Variable +200 mV overvoltage threshold, referred to VDAC reference voltage. ...
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... PM6652 8.10.6 Overcurrent protection The PM6652 controller can limit the maximum load current by skipping one or more switching cycles if the valley current limit is detected. The current limit sensing is independent from the current sensing for droop and IMON functions. Basically, the voltage drop sensed between PGND and PHASE pins, when the low side MOSFET is on, is ...
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... UV fault is detected. In order to set the right valley current limit threshold, the PM6652 internal parameters and also external components accuracy must be considered. A complete computation of the valley current limit threshold worst case variation can be ...
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... This two elements are only influenced by external components; δ ● the current sensing element (inductor's DCR or precision resistor) variation SNS due to its accuracy; δ ● V < 2 the PM6652 integrator maximum offset. OFFSET Based on Equation 7 Equation 25 The same mathematical approach provides with the following computation, based on Equation 11 : and Equation 9 , the programmed output voltage is given by: − ...
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... OUT 2 2 ⎞ ⎛ ⎞ V ⎟ ⎟ ⎜ ⎟ + IMON , off + ⎜ ⎟ ⋅ ⋅ ⎠ ⎝ ⎠ SNS SNS OUT Equation 26 for details). ) and by the current sensing element PM6652 2 ⎛ δ ⎞ G ⎜ ⎟ SNS ⎜ ⎟ ⎝ G ⎠ SNS ...
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... PM6652 Equation 30 δ given V the voltage drop across the current sensing filter resistor, due to the CSNS pin LKG leakage current (see δ δ IMON , STAT + IMON IMON IMON SNS Equation 13 ). Doc ID 16867 Rev 3 Device description δ LKG TH ⋅ ⋅ SNS L SNS ...
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... ⎜ ⋅ ⎟ ⎟ ⋅ ⎟ ⎟ ⎜ SNS + ⋅ ⋅ ⎠ ⎝ ⎠ ⋅ = ⋅ DCR SNS ⋅ ⋅ ⋅ ⋅ DCR + ⋅ ⋅ + ⋅ ⋅ the high frequency sensed current DCR . PP and C 34 PM6652 ( ) since 15 ...
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... PM6652 Following waveforms provide a “visual” approach useful to understand the relationship between the load transient response and the two capacitance values. Figure 43. C15 good and C34 OK Figure 45. C15 small and C34 OK Figure 47. C15 good and C34 big Figure 44. C15 big and C34 OK Figure 46 ...
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... Application ideas 9.2 Voltage regulation without droop PM6652 can be suitable also for high current DC/DC conversion requiring high precision load regulation and no load line function. Figure 49. No load-line output reference schematic 1 2 SVCC C30 8 SVCC Figure 49 the typical current sensing filter (R31, C15) has been modified by adding C60 and R32, in order to disable the load-line (or droop) function ...
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... PM6652 Equation 35 If C60 is used in the current sensing network the IMON function and the average current limit feature are not available, since the DC sensed current is almost equal to zero (see Section 8.10.2: Current monitor (IMON) on page 35 This application idea has been verified for IMVP7 VCCIO and PCH core supply, 1.05 V rail. ...
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... A few waveforms show the AC behavior during load transient (from 150 ns), with different load transient frequency. Figure 53. Load transient response - 5 kHz Figure 55. Load transient response - 100 kHz 48/53 Figure 52. VCCIO output voltage ripple (16 A) Figure 54. Load transient response - 40 kHz Figure 56. Load transient response - 300 kHz Doc ID 16867 Rev 3 PM6652 ...
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... PM6652 10 Layout guidelines The PM6652 has two separate grounds: PGND, the power ground, and SGND, the reference for IC internal circuitry separate grounds layout is based on the following guidelines: ● Design an analog/signal ground plane on one inner layer, connect this area to SGND and exposed pad (trough some vias); ...
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... VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead. Very thin 1.00 mm max. 50/53 (mm) Min. Typ. 0.80 0.90 0 0.02 0.20 0.18 0.25 4.85 5.00 2.90 3.10 4.85 5.00 2.90 3.10 0.50 0.30 0.40 Doc ID 16867 Rev 3 PM6652 ® www.st.com. Max. 1.00 0.05 0.30 5.15 3.20 5.15 3.20 0.50 0.05 ...
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... PM6652 Figure 57. VFQFPN 5x5x1.0 mm 32L pitch 0.50 mechanical drawing Doc ID 16867 Rev 3 Package mechanical data 51/53 ...
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... Document revision history Date 04-Dec-2009 28-Jan-2010 26-May-2010 52/53 Revision 1 Initial release Updated coverpage, and Section 8 on page 25 2 Added Figure 2 on page 7 3 Added Section 9: Application ideas on page 44 Doc ID 16867 Rev 3 Changes Table 2 on page 11, Table 4 on page 12 and Figure 3 on page 8 PM6652 ...
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... PM6652 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...