PM6652 STMicroelectronics, PM6652 Datasheet - Page 49

• Manufacturer Part Number: PM6652
• Description: IC CTLR STEPDOWN SMPS 32VFQFPN
• Manufacturer: STMicroelectronics

Specifications of PM6652

• Applications: Controller, Intel IMVP-6.5™, VR11
• Voltage - Input: 4.5 V ~ 36 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 V ~ 1.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PM6652
10
Layout guidelines
The PM6652 has two separate grounds: PGND, the power ground, and SGND, the
reference for IC internal circuitry. A 2 separate grounds layout is based on the following
guidelines:
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Alternatively, a single ground PCB can be designed, taking into account the following
suggestions (refer to
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Other suggestions for a good layout follow:
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Design an analog/signal ground plane on one inner layer, connect this area to SGND
and exposed pad (trough some vias);
Design one power ground plane on one internal layer. Connect the SGND (signal
ground) plane and PGND plane in one point (ex. under exposed pad or near the low-
side MOSFET source). If PGND plane and SGND plane are in different layers, use at
least 2 vias for the connection. It is recommended not to use a resistor to connect
PGND plane and SGND plane.
Design one power ground plane on one internal layer;
Connect all the components referred to SGND (R15, C2, C6, C8, R10, C9) with a
dedicated trace, then connect this trace to SGND (pin 9) and to the IC thermal pad;
Connect the IC thermal pad directly to the power ground, through some vias.
GSNS, VSNS: Route the remote feedback sensing nets coupled (7 mils separation)
and 18 mils wide. Keep 25 mils separation from other signals (this is an Intel
suggestion);
CSNS, VOUT: Keep the current sensing signals directly from the current sensing
element terminals (inductor pads, for DCR sensing, or precision resistor pads). Place
the L-DCR filter, if required, near the inductor and route the current sensing nets
coupled and far from noisy nets. Place the NTC thermistor, if required, as close as
possible to the inductor. Use the GND/SGND plane for shielding.
IMON, IMONFB: Keep far from switching traces (use, if necessary, the GND/SGND
plane for shielding) and place the output R-C filter close to the CPU;
LGATE, HGATE, PHASE: Design trace width > 20 mils and as short as possible (avoid
using vias if possible). Keep the ratio 3 mils_width/100 mils_lenght even for traces
longer than 500 mils (Ex. trace length: 2000 mils. design a trace width of about
60 mils). Keep far from signal traces to avoid noise coupling on signal traces. Place the
gate resistor near the MOSFET gate.
BOOT: Place ceramic capacitor close to BOOT pin and PHASE pin; the trace must be >
20 mils and the spacing with other signal trace > 20 mils. Minimize the length of the
loop between PHASE pin and BOOT pin. Use at least 3 vias if a layer change is
required.
SVCC, PVCC: Place the capacitor close to SVCC/PVCC pin. Design trace width >=
20 mils. SVCC is internally connected to PVCC through a few Ω resistor (3 Ω, typ.) so
SVCC doesn't need to be externally connected to +5 V rail.
Figure 1 on page 7
Doc ID 16867 Rev 3
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Layout guidelines
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