ISL62882HRTZ-T Intersil, ISL62882HRTZ-T Datasheet - Page 4

• Manufacturer Part Number: ISL62882HRTZ-T
• Description: IC REG PWM 2PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62882HRTZ-T

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Pin Descriptions
ISL62882 ISL62882B
31 thru 37
pad
24
25
26
27
28
29
30
38
39
40
-
-
38 thru 44
pad
29
30
32
33
34
35
36
45
46
47
48
-
VID0 thru VID6
4
DPRSLPVR
CLK_EN#
SYMBOL
LGATE1b
BOTTOM
PHASE2
UGATE2
LGATE1
LGATE2
BOOT2
VR_ON
VSSP2
VCCP
NC
ISL62882, ISL62882B
be pulled low when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to
the gate of the Phase-1 low-side MOSFET that is idle in deeper sleep mode.
the gate of the Phase-1 low-side MOSFET.
Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin.
Decouple with at least 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins
respectively.
the gate of the Phase-2 low-side MOSFET.
Current return path for the Phase-2 converter low-side MOSFET gate driver.
Connect the VSSP2 pin to the source of the Phase-2 low-side MOSFET through a
low impedance path, preferably in parallel with the trace connecting the LGATE2
pin to the gate of the Phase-2 low-side MOSFET.
Current return path for the Phase-2 high-side MOSFET gate driver. Connect the
PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor of Phase-2.
the gate of the Phase-2 high-side MOSFET.
Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot
capacitor is charged through an internal boot diode connected from the VCCP pin
to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage
dropped across the internal boot diode.
Voltage regulator enable input. A high level logic signal on this pin enables the
regulator.
Deeper sleep enable signal. A high level logic signal on this pin indicates that the
microprocessor is in deeper sleep mode.
Open drain output to enable system PLL clock. It goes low 13 switching cycles
after Vcore is within 10% of Vboot.
No connect.
IC.
Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will
Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to
Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to
Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to
VID input with VID0 = LSB and VID6 = MSB.
The bottom pad of ISL62882B is electrically connected to the GND pin inside the
(Continued)
DESCRIPTION
FN6890.3