ISL62883HRTZ Intersil, ISL62883HRTZ Datasheet - Page 21

• Manufacturer Part Number: ISL62883HRTZ
• Description: IC REG PWM 3PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62883HRTZ

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 21 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where N is the number of phases.
Transfer function A
inductor DCR value increases as the winding temperature
increases, giving higher reading of the inductor DC
current. The NTC R
temperature decreases. Proper selections of R
R
inductor total DC current over the temperature range of
interest.
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the
NTC network and the R
divider, V
voltage. It is recommended to have a higher ratio of V
to the inductor DCR voltage, so the droop circuit has
higher signal level to work with.
A typical set of parameters that provide good
temperature compensation are: R
R
(ERT-J1VR103J). The NTC network parameters may
need to be fine tuned on actual boards. One can apply
full load DC current and record the output voltage
reading immediately; then record the output voltage
reading again when the board has reached the thermal
steady state. A good NTC network can limit the output
voltage drift to within 2mV. It is recommended to follow
the Intersil evaluation board layout and current-sensing
network parameters to minimize engineering time.
V
controller to achieve good transient response. Transfer
function A
to match ω
frequencies. By forcing ω
the solution, Equation 24 gives Cn value.
FIGURE 15. DESIRED LOAD TRANSIENT RESPONSE
ω
p
p
Cn
C
sns
n
and R
= 11kΩ, R
(s) also needs to represent real-time I
=
=
-------------------------------------------------------------- -
R
------------------------------------------
R
ntcnet
ntcnet
--------------------------------------------------------
R
------------------------------------------
R
ntc
cn
ntcnet
ntcnet
cs
L
is always a fraction of the inductor DCR
(s) has a pole ω
parameters ensure that V
and ω
ntcs
WAVEFORMS
×
+
R
-------------- -
R
-------------- -
×
+
L
sum
sum
1
R
-------------- -
N
N
R
-------------- -
= 2.61kΩ and R
sum
sum
sns
N
N
cs
ntc
×
(s) always has unity gain at DC. The
DCR
×
so A
values decreases as its
sum
C
L
n
21
cs
equal to ω
sns
resistors form a voltage
V o
o i
(s) is unity gain at all
and a zero ω
ntc
sum
sns
= 10kΩ
Cn
= 3.65kΩ,
and solving for
represent the
o
ISL62883, ISL62883B
(s) for the
L
. One needs
sum
(EQ. 23)
(EQ. 24)
, R
ntcs
cn
,
For example, given N = 3, R
R
L = 0.36µH, Equation 24 gives C
Assuming the compensator design is correct, Figure 15
shows the expected load transient response waveforms
if C
has a square change, the output voltage V
a square response.
If C
accurately represent real-time I
transient response. Figure 16 shows the load transient
response when C
upon load insertion and may create a system failure.
Figure 17 shows the transient response when C
large. V
There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU
reliability.
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 17. LOAD TRANSIENT RESPONSE WHEN C
FIGURE 18. OUTPUT VOLTAGE RING BACK PROBLEM
ntcs
n
n
is correctly selected. When the load current I
value is too large or too small, V
= 2.61kΩ, R
core
is sluggish in drooping to its final value.
IS TOO SMALL
IS TOO LARGE
BACK
RING
n
ntc
o i
is too small. V
= 10kΩ, DCR = 0.88mΩ and
L i
o i
V o
V o
o i
sum
o
= 3.65kΩ, R
n
(s) and will worsen the
core
V o
= 0.406µF.
will sag excessively
Cn
(s) will not
core
p
= 11kΩ,
n
also has
is too
FN6891.3
core
n
n