IP1827TRPBF International Rectifier, IP1827TRPBF Datasheet - Page 14

• Manufacturer Part Number: IP1827TRPBF
• Description: IC DC-DC REG SYNC BUCK LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of IP1827TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 12 V
• Current - Output: 25A
• Frequency - Switching: 225kHz ~ 1.65MHz
• Voltage - Input: 1.5 V ~ 16 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Package: LGA - 7.7 x 7.7
• Circuit: Single Output
• Iout (a): 25
• Switch Freq (khz): 250 - 1500
• Input Range (v): 1.5 - 16
• Output Range (v): 0.6 - 0.75*Vin
• Internal Bias Ldo: Yes
• Ocp Otp Uvlo Pre-bias Soft Start And: Remote Sense + Body Tracking + Temp Comp OCP
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRE‐BIAS STARTUP
iP1827 is able to start up into pre‐charged output,
which prevents oscillation and disturbances of the
output voltage.
The output starts in asynchronous fashion and keeps the
synchronous MOSFET off until the first gate signal for
control MOSFET is generated, following which, the
synchronous MOSFET starts with a narrow duty cycle of
12.5% and gradually increases its duty cycle in steps of
12.5%, with 32 cycles at each step until the end of pre‐bias.
E nable Threshold = 1.2V
Figure 7b: Recommended startup sequence
Figure 7a: Normal Start up, Device turns on
14
when the Bus voltage reaches 10.2V
V in = 10.2 V
January 24, 2011 | V1.2
with Vcc or PVcc
PVcc(5V) or Vcc(3.3V)
Bus Voltage (12V)
Bus Voltage (12V )
V cc(5V )
Enable > 1.2V
E nable
Highly Integrated 25A Single‐input Voltage,
SS
S S
Synchronous Buck Regulator
At the end of the pre‐bias stage, the synchronous MOSFET
is switched complementary to the Control MOSFET.
Figure 8 shows a typical Pre‐Bias condition at start up.
SOFT‐START
The iP1827 has a programmable soft‐start to control the
output voltage rise and to limit the current surge at the
start‐up. To ensure correct start‐up, the soft‐start
sequence initiates when the Enable and Vcc rise above
their UVLO thresholds and generate the Power On Ready
(POR) signal. The internal current source (typically 20uA)
charges the external capacitor Css linearly from 0V to Vcc.
Figure 10 shows the waveforms during the soft start.
The start up time can be estimated by:
During the soft start the OCP is enabled to protect the
device for any short circuit and over current condition.
12.5%
T
start
P re -B ia s
32
V o lta g e
LDRiss
[V ]
HDRv
LDRv


...
...
Figure 9: Pre‐Bias startup pulses
0.8
Figure 8: Pre‐Bias startup
-
0.2
...
I
ss

32
*
25%
C
SS
...
...
... ...
...
... ...
87.5%
32
...
iP1827
[T im e ]
V o
...
(1)
97599
End of
PB