IP1827TRPBF International Rectifier, IP1827TRPBF Datasheet - Page 17

• Manufacturer Part Number: IP1827TRPBF
• Description: IC DC-DC REG SYNC BUCK LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of IP1827TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 12 V
• Current - Output: 25A
• Frequency - Switching: 225kHz ~ 1.65MHz
• Voltage - Input: 1.5 V ~ 16 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Package: LGA - 7.7 x 7.7
• Circuit: Single Output
• Iout (a): 25
• Switch Freq (khz): 250 - 1500
• Input Range (v): 1.5 - 16
• Output Range (v): 0.6 - 0.75*Vin
• Internal Bias Ldo: Yes
• Ocp Otp Uvlo Pre-bias Soft Start And: Remote Sense + Body Tracking + Temp Comp OCP
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In applications where only local sensing is required for
feedback, the remote voltage sensing pins of the iP1827
may be dedicated to sensing the output for power good
indication and overvoltage protection.
POWER GOOD OUTPUT AND
OVER‐VOLTAGE PROTECTION
The IC continually monitors the output voltage via output
of the remote sense amplifier (Voso pin). The Voso voltage
forms an input to a window comparator whose upper and
lower thresholds are 0.7V and 0.51V respectively. Hence,
the Power Good signal is flagged when the Voso pin
voltage is within PGood window, i.e., between 0.51V and
0.69V, as shown in Figure 12a. The PGood pin is open drain
and it needs to be externally pulled high. High state
indicates that output is in regulation. Figure 12a also shows
the PGood timing diagram with a 256 cycle delay between
the Voso voltage entering within the thresholds defined by
the PGood window and PGood going high
If the output voltage exceeds the over voltage threshold
0.7V, an over voltage trip signal is asserted; this will turn
off the high side driver and turn on the low side driver until
the Voso voltage drops below the 0.7V threshold. Both
drivers are then turned off until a reset is performed by
cycling Vcc (or PVcc/Enable) or until another OVP event
occurs turning on the low side driver again.
Figure 12b shows the response in over‐voltage condition.
0
0
0
Voso
SS
PGD
0.2V
Figure 12a: iP1827 Power Good Signal Timing Diagram
0.8V
17
256/Fs
January 24, 2011 | V1.2
0.51V
256/Fs
0.7V
Highly Integrated 25A Single‐input Voltage,
Synchronous Buck Regulator
BODY BRAKING
The Body Braking feature of the iP1827 allows improved
transient response to step‐down load transients. A severe
step‐down load transient would cause an overshoot in the
output voltage and drive the Comp pin voltage down until
control saturation occurs demanding 0% duty cycle, and
the PWM input to the Control FET driver is kept OFF. When
the first such skipped pulse occurs, the iP1827 enters the
Body Braking mode, wherein the Sync FET is also turned
OFF. The inductor current then decays by freewheeling
through the body diode of the Sync FET. Thus, with Body
Braking, the forward voltage drop of the body diode
provides an additional voltage to discharge the inductor
current faster to the light load value as shown in equations
4 and 5 below:
where V
Sync FET.
The Body Braking mechanism is kept OFF during pre‐bias
operation. Also, in the event of an extremely severe load
step‐down transient causing an OVP, the Body Brake is
overridden by the OVP latch, which turns on the Sync FET.
HDrv
LDrv
Voso
PGood
SS
0
0
0
0
0
di
di
dt
dt
L
L
D
= forward voltage drop of the body diode of the


Figure 12b: iP1827 Signal Timing for OVP


V
V
L
o
o
,

L
without
TM
V
D
,
0.7V
with
body
body
braking
braking
iP1827
0.6V
(4)
(5)
97599