AD9880/PCBZ Analog Devices Inc, AD9880/PCBZ Datasheet - Page 47

• Manufacturer Part Number: AD9880/PCBZ
• Description: KIT EVALUATION AD9880
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9880/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9880
• Primary Attributes: Analog & HDMI/DVI Dual Display Interface
• Secondary Attributes: Auto-Offset, Color Space Converter, RGB and YCbCr Output Formats
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5281026

0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
Table 64. CTRL Enable.
Select
0
1
0x2E
Table 65. I2S Output Select
I2S Output Mode
00
01
10
11
0x2E
0x2F
See the line width MSBs section.
1-0
Along with the eight bits following these ten bits set
the delay (in pixels) from the Hsync leading edge to
the start of active video. The power-up default setting
is 0x104.
7-0
See the Hsync Delay MSBs section.
3-0
Along with the 8 bits following these 12 bits, set the
width of the active video line (in pixels). The power-
up default setting is 0x500.
7-0
3-0
Along with the 8 bits following these 12 bits, set the
height of the active screen (in lines). The power-up
default setting is 0x2D0.
7-0
See the Screen Height MSBs section.
7
When set, this bit allows Ctrl [3:0] signals decoded
from the DVI to be output on the I2S data pins. The
power-up default setting is 0.
6-5
These bits select between four options for the I2S
output: I2S, right-justified, left-justified, or raw
IEC60958 mode. The power-up default setting is 00.
4-0
These bits set the I2S bit width for right-justified
mode. The power-up default setting is 24 bits.
6
This read-only bit indicates the presence of a TMDS
DE.
Hsync Delay MSBs
Hsync Delay LSBs
Line Width MSBs
Line Width LSBs
Screen Height MSBs
Screen Height LSBs
Ctrl Enable
I2S Output Mode
I2S Bit Width
TMDS Sync Detect
Result
I2S signals on I2S lines
Ctrl [3:0] output on I2S lines
Result
I2S mode
Right-Justified
Left-Justified
Raw IEC60958 mode
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Table 66. Detected TMDS Sync Results
Detect
0
1
0x2F
Table 67. Detected TMDS Clock Results
Detect
0
1
0x2F
Table 68. Detected AV Mute Status
Detect
0
0x2F
Table 69. HDCP Keys
Detect
0
1
0x2F
0x30
Table 70. HDCP Activity
Detect
0
1
0x30
5
This read only bit indicates the presence of a TMDS
clock.
4
This read-only bit indicates the presence of AV (audio
video) mute based on general control packets.
3
This read-only bit reports if the HDCP keys were read
successfully.
2-0
These read-only bits indicate a level of HDMI quality
based on the DE (display enable) edges. A larger
number indicates a higher quality.
6
This read-only bit is high when HDCP decryption is
in use (content is protected). The signal goes low
when HDCP is not being used. Customers can use this
bit to determine whether or not to allow copying of
the content. The bit should be sampled at regular
intervals since it can change on a frame by frame
basis.
5
This read-only bit indicates the polarity of the DVI
Hsync.
TMDS Active
AV Mute
HDCP Keys Read
HDMI Quality
HDMI Content Encrypted
DVI Hsync Polarity
Result
No TMDS DE present
TMDS DE detected
Result
No TMDS clock present
TMDS clock detected
Result
AV not muted
AV muted
Result
Failure to read HDCP keys
HDCP keys read
Result
HDCP not in use
HDCP decryption in use
AD9880