KDC5512HEVALZ Intersil, KDC5512HEVALZ Datasheet - Page 26

• Manufacturer Part Number: KDC5512HEVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512HEVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512HP has a selectable clock divider that can be
set to divide by four, two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input
Considerations” on page 31). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512HP can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive strength
in LVDS mode can be set high (3mA) or low (2mA). By
default, the tri-level OUTMODE pin selects the mode and
drive level (refer to “Digital Outputs” on page 20). This
functionality can be overridden and controlled through the
SPI, as shown in Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 21). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
TABLE 11. CLOCK DIVIDER SELECTION
TABLE 13. OUTPUT FORMAT CONTROL
VALUE
VALUE
TABLE 12. OUTPUT MODE CONTROL
VALUE
000
001
010
100
000
001
010
100
000
001
010
100
26
OUTPUT FORMAT
Two’s Complement
CLOCK DIVIDER
OUTPUT MODE
Offset Binary
Pin Control
Divide by 1
Divide by 2
Divide by 4
Pin Control
Gray Code
0x72[2:0]
0x93[2:0]
Pin Control
LVDS 2mA
LVDS 3mA
0x93[7:5]
LVCMOS
KAD5512HP
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Bit 4 DDR Enable
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 14 shows
the allowable sample rate ranges for the slow and fast
settings.
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
The procedure for setting output_mode_B is shown in
Figure 40. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
OUTPUT_MODE_B
CONFIG_STATUS
DLL RANGE
This bit sets the DLL operating range to fast (default) or
slow.
Setting this bit enables Double Data-Rate mode.
FIGURE 40. SETTING OUTPUT_MODE_B REGISTER
Slow
Fast
READ
READ
0x74
0x75
TABLE 14. DLL RANGES
DESIRED
VALUE
MIN
40
80
f
S
MAX
100
MAX
WRITE TO
October 1, 2009
MSPS
MSPS
UNIT
0x74
FN6808.3