ISL6420BEVAL2Z Intersil, ISL6420BEVAL2Z Datasheet - Page 3

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ISL6420BEVAL2Z

Manufacturer Part Number
ISL6420BEVAL2Z
Description
EVAL BOARD 2 FOR ISL6420B
Manufacturer
Intersil
Datasheets

Specifications of ISL6420BEVAL2Z

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Performance
Switching Frequency
The evaluation board has a 0Ω resistor R9 connecting RT
to VCC5 setting the free-running switching frequency to
300kHz. The frequency can be programmed to a
different value by removing R9 and populating the R5
location with a resistor value based on the desired
frequency.
Output Ripple
Figure 7 shows the ripple voltage on the output of the
regulator at the free running 300kHz frequency.
Efficiency
ISL6420B-based regulators enable the design of highly
efficient systems. The efficiency of the evaluation board
using a 12V, 18V and 24V input supply, as shown in
Figure 8.
The load regulation of the evaluation board using a 12V,
18V and 24V input supply is shown in Figure 9.
FIGURE 8. EVALUATION BOARD EFFICIENCY
96
94
92
90
88
86
84
82
80
78
76
74
72
70
1
V
IN
(V
= 12V
FIGURE 7. OUTPUT RIPPLE
OUT
2
= 3.3V)
3
OUTPUT CURRENT (A)
4
V
3
V
IN
IN
5
= 24V
= 18V
6
7
V
OUT
Application Note 1504
8
9
10
Power Good
PGOOD will be true (open drain) when the FB pin voltage
is within ±10% of the reference voltage and the soft-
start sequence is complete, i.e., once the soft-start
capacitor is finished charging. The assertion of PGOOD
signal can be delayed by a time proportional to a CDEL
current of 2µA and the value of the capacitor connected
between this pin and ground.The status of PGOOD can
be monitored at the PGOOD test point (TP1).
Overcurrent Protection
The overcurrent function cycles the soft-start function in
a hiccup mode to provide fault protection. Figure 11
shows the overcurrent hiccup mode.
The overcurrent function protects the converter from a
shorted output by using the upper MOSFET’s r
monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
FIGURE 9. EVALUATION BOARD LOAD REGULATION
3.33
3.32
3.31
3.30
3.29
0
V
IN
(V
1
= 12V
OUT
V
IN
FIGURE 10. PGOOD
2
= 3.3V)
= 24V
OUTPUT CURRENT (A)
3
V
4
IN
= 18V
5
6
7
PGOOD
November 23, 2009
8
CDEL
DS(ON)
9
V
ENSS
AN1504.0
OUT
10
to

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